2-D Compact Model for Drain Current of Fully Depleted Nanoscale GeOI MOSFETs for Improved Analog Circuit Design

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

“…Thus the value of minimum surface potential is obtained as where A, B and k are given in the appendix. Quantitatively the threshold voltage (V th ) for a GAA MOSFET refers to the minimum applied voltage on the gate terminal at which the minimum inversion carrier density (Q inv ) reaches its threshold value (Q th ) required for identifying the turn-on condition [5,31,32]. This definition of V th is identical to the constantcurrent method of measurement vastly used in numerical simulations [33].…”

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

“…However, Ge CMOS device is more susceptible to short-channel effect (SCE) due to the high permittivity of Ge [5] and strong fringing-field effect (FFE) that resulted from highk gate dielectric [6]. To overcome these issues, MOSFETs with ultrathin-body (UTB) and thin buried oxide are proposed as a promising device structure for high-speed circuits with 10-nm-order gate length [7] because the structure holds high immunity to threshold-voltage variability and better control of SCE [8][9][10]. As an important electrical parameter, the threshold voltage of the devices has been studied extensively.…”