2014 Symposium on VLSI Circuits Digest of Technical Papers 2014
DOI: 10.1109/vlsic.2014.6858415
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2<sup>nd</sup> generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology

Abstract: 2nd generation lGbit 2GHz Embedded DRAM (eDRAM) with 4X lower self refresh power compared to prior generation is developed in 22nm Tri-Gate CMOS technology. Retention time has been improved by 3X (300us@95°C) by process and design optimizations. Source synchronous clocking is integrated in the design to reduce clock power without penalizing bandwidth.Charge pump power is reduced by 4X by employing comparator based regulation. Temperature controlled refresh enables minimum refresh power at all temperature condi… Show more

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Cited by 5 publications
(3 citation statements)
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“…We show the published cell size for all technologies discussed above in figure 1(c), i.e. SRAM [46][47][48][49][50][51][52][53], eDRAM [54][55][56][57][58][59], eFlash [60][61][62][63][64][65][66][67], DRAM [41,68], eReRAM [69][70][71][72][73], STT-MRAM [42,[74][75][76][77][78][79][80][81][82][83][84][85][86][87]. Note that the SRAM cell sizes down to 7 nm are from literature while the cell sizes (F 2 ) for 3 and 5 nm are linear extrapolation based on the cell sizes from 22 nm to 7 nm.…”
Section: Scaling Analysismentioning
confidence: 99%
“…We show the published cell size for all technologies discussed above in figure 1(c), i.e. SRAM [46][47][48][49][50][51][52][53], eDRAM [54][55][56][57][58][59], eFlash [60][61][62][63][64][65][66][67], DRAM [41,68], eReRAM [69][70][71][72][73], STT-MRAM [42,[74][75][76][77][78][79][80][81][82][83][84][85][86][87]. Note that the SRAM cell sizes down to 7 nm are from literature while the cell sizes (F 2 ) for 3 and 5 nm are linear extrapolation based on the cell sizes from 22 nm to 7 nm.…”
Section: Scaling Analysismentioning
confidence: 99%
“…Commodity DDR3 (2007) [14]; DDR4 (2012) [18] Low-Power LPDDR3 (2012) [17]; LPDDR4 (2014) [20] Graphics GDDR5 (2009) [15] Performance eDRAM [28], [32]; RLDRAM3 (2011) [29] 3D-Stacked WIO (2011) [16]; WIO2 (2014) [21]; MCDRAM (2015) [13]; HBM (2013) [19]; HMC1.0 (2013) [10]; HMC1.1 (2014) [11] Academic SBA/SSA (2010) [38]; Staged Reads (2012) [8]; RAIDR (2012) [27]; SALP (2012) [24]; TL-DRAM (2013) [26]; RowClone (2013) [37]; Half-DRAM (2014) [39]; Row-Buffer Decoupling (2014) [33]; SARP (2014) [6]; AL-DRAM (2015) [25] At the forefront of such innovations should be DRAM simulators, the software tool with which to evaluate the strengths and weaknesses of each new proposal. However, DRAM simulators have been lagging behind the rapid-fire changes to DRAM.…”
Section: Segment Dram Standards and Architecturesmentioning
confidence: 99%
“…The eDRAM die consumes less than 1.5 W at self-refresh mode and less than 5 W at peak 128 GB/s bandwidth, including OPIO. The power consumption is greatly improved in our second-generation eDRAM design through various process, circuit, and architectural innovations [10]. Fig.…”
Section: Operating Voltage and Frequencymentioning
confidence: 99%