20 ${\hbox{kA/cm}}^{2}$ Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency

Abstract

Results of the development of an advanced fabrication process for superconductor integrated circuits (ICs) with 20 kA cm 2 Nb AlO x Nb Josephson junctions is presented. The process has 4 niobium superconducting layers, one MoN x resistor layer with 4.0 Ohm per square sheet resistance for the junction shunting and circuit biasing, and employs circular Josephson junctions with the minimum diameter of 1 m; total 11 photolithography levels. The goal of this process development is the demonstration of the feasibility of 80 GHz clock speeds in superconducting ICs for digital signal processing (DSP) and high performance computing. Basic components of Rapid Single Flux Quantum (RSFQ) logic such as DC/SFQ, SFQ/DC converters, Josephson transmission lines (JTLs), and simple digital circuits such as T-flip-flops and 4-bit digital counters have been fabricated and tested. The T-flip-flops were shown to operate up to 400 GHz with the widest margin of operation of 13% at 325 GHz. Digital testing results on the 4-bit counters as well as the junctions, resistors, and other process parameters are also presented. Prospects for yet higher speeds and very large scale integration are discussed.

Electrical stress effect on Josephson tunneling through ultrathin AlOx barrier in Nb/Al/AlOx/Nb junctions

“…[18,23] The fabrication was performed on 150-mm Si wafers. The process is based on in-situ Nb/Al/AlO x /Nb trilayer deposition.…”

“…[17] Increasing the clock frequencies of superconductor integrated circuits to ∼ 100 GHz would require employing high-J c junctions with RA products below ∼1 Ω · µm 2 , perhaps the thinnest tunnel barriers among all known devices. [18,19] Dielectric reliability may not appear to be important for superconducting digital circuits because they operate at very low temperatures and at very low voltages (∼1 mV). Its significance however arises from the possibility that tunnel barrier degradation may occur during integrated circuit fabrication.…”

“…For instance, the current state of the art in RSFQ circuits has been plagued by limited circuit yield brought about to a large extent by fabrication-induced variations on the Josephson critical current (I c ) of the tunnel junctions. [18,20] These variations may be related to dielectric barrier degradation and electrical breakdown. It has been observed, for example, that the I c of Josephson tunnel junctions may depend on how the junction is wired to other circuit elements, and in particular, at which step in the fabrication process the junction makes electrical contact with the circuit's ground plane.…”

Diffusion Stop-Layers for Superconducting Integrated Circuits and Qubits With Nb-Based Josephson Junctions

“…Our standard 11-layer fabrication process was described in detail in [16], [17]. Its cross-section is presented in Fig.…”

Note: Increasing dynamic range of digital-to-analog converter using a superconducting quantum interference device

“…[3][4][5][6][7] Output voltage from a JJ array or a programmable JJ array, in principle, has quantum accuracy and is used as quantum standard of voltage, because the induced voltage (U) is directly proportional to frequency (f) of microwave: U = n o f, where o = h/2e 2.067 × 10 −15 Wb, h is Planck's constant, e is the elementary charge, and n is an integer. [8][9][10][11][12][13][14][15] They can be used as DACs, however, ratio of maximum output voltage to voltage interval or dynamic range for these devices is around 50 000 because the interval or least significant bit is not easily adjustable.…”