Diffusion Stop-Layers for Superconducting Integrated Circuits and Qubits With Nb-Based Josephson Junctions

Tolpygo, Sergey K.; Amparo, Denis; Hunt, Richard A.; Vivalda, John; Yohannes, Daniel

doi:10.1109/tasc.2010.2089665

Cited by 14 publications

(6 citation statements)

References 23 publications

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“…Such an increase is known to occur in planar Nb film with decreasing their thickness and caused by decreasing electron mean free path [38]. Another causes could be Nb surface oxidation or hydrogen contamination in processing; see [45], [46] and references therein. Since Nb contamination mainly occurs through the sidewalls of the etched lines, the degree of contamination grows with decreasing the linewidth because the strip surface to volume ratio increases as 1/w.…”

Section: B Stripline Inductors With Linewidths Down To 120 Nmmentioning

confidence: 99%

Inductance of superconductor integrated circuit features with sizes down to 120 nm

Tolpygo

Golden

Weir

et al. 2021

Supercond. Sci. Technol.

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Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers and composite vias between distant superconducting layers. Effects of magnetic flux trapping in ground plane moats on coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations. Test circuits used for the measurements were fabricated in a new 150-nm node of a fully planarized process with eight niobium layers, SC2 process, developed at MIT Lincoln Laboratory for superconductor electronics and in its 250nm node SC1, as well as in the standard fabrication process SFQ5ee. The SC2 process utilizes 193-nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. All other processes use 248-nm photolithography. Effects of variation of process parameters on circuit inductors are discussed. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Part II is devoted to mutual inductance of various closely spaced features in integrated circuits, meanders, and transformers.

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Section: B Stripline Inductors With Linewidths Down To 120 Nmmentioning

confidence: 99%

Inductance of superconductor integrated circuit features with sizes down to 120 nm

Tolpygo

Golden

Weir

et al. 2021

Supercond. Sci. Technol.

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show abstract

“…This needs further investigating as well as finding the methods of eliminating this contamination. We note here that hydrogen diffusion barriers proposed and implemented in [11] do not eliminate hydrogen contamination of Nb but simply fix the hydrogen content by preventing hydrogen migration between the circuit layers. As can be seen, the difference between the JJs with hydrogen and without hydrogen can reach ~ 10%.…”

Section: Hydrogen Effect On Critical Current and J C Targetingmentioning

confidence: 99%

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

Tolpygo

Bolkhovsky

Weir

et al. 2016

IEEE Trans. Appl. Supercond.

213

111

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“…The first STEM details the active area with the four top un-planarized layers with the emphasis to the anodized Josephson junction and the bias resistor. The second STEM includes the planarized layers with an aluminum-free via plugs, A layer introduced to stop the diffusion of hydrogen [21], [22] and a passivation layer on top of M3 layer.…”

Section: B Diagnostics Test Resultsmentioning

confidence: 99%

Planarized, Extendible, Multilayer Fabrication Process for Superconducting Electronics

Yohannes

Hunt

Vivalda

et al. 2015

IEEE Trans. Appl. Supercond.

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We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of aluminum as an etch stop in the metal-via stack. The drawback of the previous approach was the difficulty in processing aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm 2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/−22%.

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Diffusion Stop-Layers for Superconducting Integrated Circuits and Qubits With Nb-Based Josephson Junctions

Cited by 14 publications

References 23 publications

Inductance of superconductor integrated circuit features with sizes down to 120 nm

Inductance of superconductor integrated circuit features with sizes down to 120 nm

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

Planarized, Extendible, Multilayer Fabrication Process for Superconducting Electronics

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