2000 V SOI LDMOS with new drift structure for HVICs

Okawa, Takashi; Eguchi, Hiroomi; Taki, Masato; Hamada, Keisuke

doi:10.1109/ispsd.2016.7520871

Cited by 13 publications

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These parameters lead to a different tradeoff between performance and device reliability. HCD can be used as it tests the N-EDMOS robustness due to the reduction in current drivability and device lifetime, induced by the source-drain resistance increase (RSD) (Figure 2c) in the drift region [14,15]. For device lifetime determination in N-EDMOS, the use of DC stressing first facilitates the distinction between worst-case damage mechanisms [8][9][10].…”

Section: The Spad Cell With Edmos Transistormentioning

confidence: 99%

“…The optimization of the EDMOS architecture depends on several factors, such as the gate-oxide thickness (T ox ), the lateral isolation by locally oxidized silicon (LOCOS) or by a shallow trench isolation (STI) [13,14]. It is also strongly related to the silicon [11] or silicon on insulator (SOI) substrate [15,16], the presence of a body buried layer [17] and the use of super junction [18]. These parameters lead to a different tradeoff between performance and device reliability.…”

Section: The Spad Cell With Edmos Transistormentioning

confidence: 99%

Section: The Spad Cell With Edmos Transistormentioning

confidence: 99%

See 2 more Smart Citations

Hot-Carrier Damage in N-Channel EDMOS Used in Single Photon Avalanche Diode Cell through Quasi-Static Modeling

Bravaix,

Pitard,

Federspiel

et al. 2024

Micromachines

View full text Add to dashboard Cite

A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (VGS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (VGS = 0). The goal was to check an accurate device lifetime extraction using accelerated DC to AC stressing by applying the quasi-static (QS) lifetime technique. N-EDMOS device is devoted to 3D bonding with CMOS imagers obtained by an optimized process with an effective gate-length Leff = 0.25 µm and a SiO2 gate-oxide thickness Tox = 5 nm. The operating frequency is 10 MHz at maximum supply voltage VDDmax = 5.5 V. TCAD simulations are used to determine the real voltage and timing configurations for the device in a mixed structure of the SPAD cell. AC device lifetime is obtained using worst-case DC accelerating degradation, which is transferred by QS technique to the AC waveforms applied to N-EDMOS device. This allows us to accurately obtain the AC device lifetime as a function of the delay and load for a fixed pulse shape. It shows the predominance of the high energy hot-carriers involved in the first substrate current peak during transients.

show abstract

Section: The Spad Cell With Edmos Transistormentioning

confidence: 99%

Section: The Spad Cell With Edmos Transistormentioning

confidence: 99%

See 1 more Smart Citation

Hot-Carrier Damage in N-Channel EDMOS Used in Single Photon Avalanche Diode Cell through Quasi-Static Modeling

Bravaix,

Pitard,

Federspiel

et al. 2024

Micromachines

View full text Add to dashboard Cite

show abstract

“…Since then, many improved structures have been demonstrated. 14,[22][23][24][25][26][27][28][29][30][31][32][33][34] Today (at the end of the 2010s), many LSI foundry companies and organizations propose the access to multichip project, or the Multi-Project Wafer (MPW), as summarized in Table II. Owing to multichip projects, designers who do not have a CMOS fabrication line can obtain HV devices.…”

Section: Ldmos High-voltage Device Technologies and Their Availabilitiesmentioning

confidence: 99%

Progress and opportunities in high-voltage microactuator powering technology towards one-chip MEMS

Mita

Hirakawa

Stefanelli

et al. 2018

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

In this paper, we address issues and solutions for micro-electro-mechanical-systems (MEMS) powering through semiconductor devices towards one-chip MEMS, especially those with microactuators that require high voltage (HV, which is more than 10 V, and is often over 100 V) for operation. We experimentally and theoretically demonstrated that the main reason why MEMS actuators need such HV is the tradeoff between resonant frequency and displacement amplitude. Indeed, the product of frequency and displacement is constant regardless of the MEMS design, but proportional to the input energy, which is the square of applied voltage in an electrostatic actuator. A comprehensive study on the principles of HV device technology and associated circuit technologies, especially voltage shifter circuits, was conducted. From the viewpoint of on-chip energy source, series-connected HV photovoltaic cells have been discussed. Isolation and electrical connection methods were identified to be key enabling technologies. Towards future rapid development of such autonomous devices, a technology to convert standard 5 V CMOS devices into HV circuits using SOI substrate and a MEMS postprocess is presented. HV breakdown experiments demonstrated this technology can hold over 700 to 1000 V, depending on the layout.

show abstract