212‐Gbit/s 2:1 multiplexing selector realised in InP DHBT

Abstract

In this Letter, the authors report on the design, optimisation and electrical measurements of a new fully integrated multiplexing selector fabricated in 0.7-µm indium phosphide (InP) double-heterojunction bipolar transistor technology. All parts of the circuit were optimised to obtain 200-Gbit/s class of operation. They present electrical performances at 140 and to a record speed of 212 Gbit/s, highlighting their respective measurement challenges. The power consumption of the circuit is 0.5 and 0.8 W for a differential output amplitude of 240 and 730 mV, respectively. This selector has been successfully used as modulator driver in optical transmission experiments up to 204 Gbit/s.

Ultra-High-Speed 2:1 Digital Selector and Plasmonic Modulator IM/DD Transmitter Operating at 222 GBaud for Intra-Datacenter Applications

“…The high-speed 2:1 multiplexing selector [27], [28] was fabricated in III-V Lab's 0.7 µm indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) technology, optimized for a broad data-bandwidth up to symbol rates beyond 200 GBd. The transistors used to design and fabricate the selector have characteristic gain-bandwidth-product-related frequencies f T and f max around 400 GHz, with a DC current gain around 30 [27], [28].…”

“…In a first characterization at 212 Gb/s, with state-of-the-art 122 GHz remote sampling heads from Keysight (N1046A-12F), the SEL chip already demonstrates its performance with a signal-to-noise ratio of ∼7 and a jitter of T jitter,rms = 300 fs at an output voltage of 240 mV pp [27]. The differential output amplitude at 212 GBd can be adjusted between 240 mV ppdiff and 730 mV ppdiff , resulting in a circuit power consumption of 0.5 W and 0.8 W, respectively.…”

160-GSa/s-and-Beyond 108-GHz-Bandwidth Over-2-Vppd Output-Swing 0.5-μm InP DHBT 2:1 AMUX-Driver for Next-Generation Optical Communications

“…An 11-ps (198 4(c) shows the 3.2-V ppd -swing high-quality 100-GSa/s 100-Gb/s NRZ eye diagram measurements, while the AMUX-driver is operated in the saturated regime (320-mV pp inputs). Moreover, AMUX-driver's 160-GBd measurements were conducted using a similar setup, yet an InP DHBT 2:1 selector module was used instead of the combiner to generate 80-Gb/s 200-mV pp -amplitude input data in multiplexing two independent 40-Gb/s NRZ signals (see [20]). An 80-GHz 390-mV pp low-jitter sine wave was used as AMUX-driver's input clock.…”

0.7-$\mu$ m InP DHBT Technology With 400-GHz ${f}_{{T}}$ and ${f}_{\text{MAX}}$ and 4.5-V BVCE0 for High Speed and High Frequency Integrated Circuits

“…The integrated circuit shown in Figure 8 is composed of 48 transistors of two different sizes (5 and 7 µm-long, 0.7 µm-wide DHBTs) and has a footprint of 1.2 × 1.5 mm 2 . More information about the circuit architecture and design is presented in [16]. The high performance and fabrication yield on transistors contribute to achieve a SEL circuit yield above 75%.…”