22FFL: A high performance and ultra low power FinFET technology for mobile and RF applications

Sell, B.; Bigwood, B.; Cha, Soonwoo; Chen, Z.; Dhage, Priyanka; Fan, Philex Ming-Yan; Giraud-Carrier, Matthieu; Kar, Aditi; Karl, Eric; Ku, Chao-Ching; Kumar, Raghavan; Lajoie, T.; Lee, H.-J.; Liu, G.; Liu, S.; Ma, Yunzhe; Mudanai, S.; Nguyen, L.; Paulson, L.; Phoa, K.; Pierce, K.; Roy, Anirban; Russell, Ryan S.; Sandford, J.; Stoeger, J.; Stojanović, Nebojša; Sultana, Ayesha; Waldemer, James; Wan, Jinbo; Xu, Wenjun; Young, D.; Zhang, J.; Zhang, Y.; Bai, P.

doi:10.1109/iedm.2017.8268475

Cited by 65 publications

(15 citation statements)

References 3 publications

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“…Since DC parameters were well calibrated, G m R o of FinFETs and NSFETs were reasonable within the measured data [10], [11], [23]- [25]. F t and F max were slightly larger than the measured data [10], [11], [23]- [25] because the parasitic RC components of metal interconnects are not included in this TCAD work. But FinFETs and NSFETs would have the same metal-line configurations under the same CPP.…”

Section: Device Structure and Simulation Methodssupporting

confidence: 52%

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Yoon

Baek

2020

IEEE Access

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Analog/RF performances of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) were investigated and compared thoroughly using fully-calibrated TCAD. NSFETs have greater current drivability and gate-to-channel controllability than FinFETs under the same footprint, thus achieving larger intrinsic gain. But the cutoff frequencies (F t) of FinFETs and NSFETs are comparable due to larger gate capacitances (C gg) of NSFETs compensating DC performance improvements. Gate resistances (R g) of NSFETs are larger because of their metal gate (MG) configuration surrounding the channels, longer MG height by the topmost NS spacing region, and the bottom transistor, thus degrading maximum oscillation frequency (F max). Device design guidelines of FinFETs and NSFETs are also studied for better intrinsic gain, F t , and F max. Intrinsic gain is improved by better electrostatics, whereas F t increases by greater current drivability over C gg. For larger F max , careful device design is required to compensate between R g , C gg , output resistance, and F t. Overall, NSFETs outperform FinFETs in terms of intrinsic gain, F t , and F max , thus NSFETs are promising for analog/RF applications.

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Section: Device Structure and Simulation Methodssupporting

confidence: 52%

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Yoon

Baek

2020

IEEE Access

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“…System on Chip (SoC) application designs require the fabrication of MOSFETs with different threshold voltages (Vth) on the same wafer to best fulfill a range of system functions (e.g., high performance vs. low power). In recent Replacement Gate CMOS technologies, multiple device Vth flavors (up to six different ones [1]) are realized, typically by depositing different work function metal stacks. It is hence of interest to investigate whether a different metal work function can affect the reliability of a given dielectric stack.…”

Section: Introductionmentioning

confidence: 99%

On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI

Franco

Rzepa

et al. 2019

IEEE Trans. Device Mater. Relib.

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We investigate BTI charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals. Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work function. However, experimental data on capacitors show enhanced or reduced charge trapping at constant oxide electric field for different work function metal stacks. We ascribe this to a different chemical interaction of the metals with the dielectric, which yields different defect profiles depending on the process thermal budget, and not to the gate work function per se. This observation is confirmed by comparing BTI degradation in nMOS and pMOS Replacement Gate planar transistors with three selected work function metal stacks (representative of high-, standard, and low-Vth device flavors), and two different process thermal budgets. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework "Comphy", we also show that, on top of the unavoidable chemical interaction of different metals with the underlying SiO2/HfO2 dielectric stack, different gate work functions within a typical range of relevance (4.35-4.75eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs.

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“…Fig. 11 shows the micrograph of the chip fabricated in Intel 22-nm FinFET (22FFL) technology [42]. The transmitter architecture shown in Fig.…”

Section: ) Lo Drivermentioning

confidence: 99%

A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons

Dijk

Patra

Subramanian

et al. 2020

IEEE J. Solid-State Circuits

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Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantumcomputing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency

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22FFL: A high performance and ultra low power FinFET technology for mobile and RF applications

Cited by 65 publications

References 3 publications

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI

A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons

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