24.8 A 14nm fractional-N digital PLL with 0.14ps&lt;inf&gt;rms&lt;/inf&gt; jitter and −78dBc fractional spur for cellular RFICs

Yao, Chunhua; Loke, Wing Fai; Ni, Ronghua; Han, Yongping; Li, Haoyang; Godbole, Kunal; Zuo, Yongrong; Ko, Sangsoo; Kim, Nam-Seog; Han, Sang-Wook; Jo, Ikkyun; Lee, Joon‐Hee; Han, Juyoung; Kwon, Daehyeon; Kim, Chul‐Ho; Kim, Shinwoong; Son, Sang Won; Cho, Thomas Byunghak

doi:10.1109/isscc.2017.7870441

Cited by 10 publications

(5 citation statements)

References 6 publications

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“…From (6), for the given noise sources, there is an optimum 𝜒, to minimize 𝜎 ∆𝑡 𝑇𝐴 where 𝜒 changes according to 𝐾 𝑇𝐴 and 𝐾 𝑇,𝑇𝐴 . However, the proposed time-difference control needs large 𝐾 𝑇𝐴 to reduce the reference spur, which will be explained in Section IV.…”

Section: B Optimum Proportional Path Gainmentioning

confidence: 99%

“…Since the digital circuits have the advantage of reducing the chip area and power consumption through a low-voltage technology, all-digital PLLs with a time-to-digital converter (TDC) have been studied [3][4][5][6][7][8][9][10][11]. In the fractional-N TDCbased PLL, the high-resolution TDC with a wide dynamic range is required to cover an entire DCO cycle, which results in a large area and power.…”

Section: Introductionmentioning

confidence: 99%

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A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

et al. 2022

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This paper presents analyses of jitter and reference spur of a digital PLL using a phasefrequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock. The amplified pulse signals modulate the digitally controlled oscillator (DCO) frequency. The TA input-referred jitter limits the minimum PFD-TA PLL output jitter in case of the low DCO and reference clock jitter. However, the PFD-TA PLL achieves a lower output jitter than the BBPLL especially when the input noise is worsened by the poor DCO, which, indeed, is common in low-power and IoT applications for lower cost and power. The reference spur caused by the path mismatches of the proposed DCO modulation is analyzed by Fourier Series, and implementing the high-gain (>100) TA reduces the reference spur with the smaller DCO modulating signal distortion. To assist the narrow input dynamic range (<30ps) of the TA, a 7-bit phase interpolator (PI) is implemented to fractional frequency divider with a PI nonlinearity calibration. The theoretical predictions are compared with the behavioral simulations and verified in measurements where the chip is fabricated in a 40 nm CMOS process, and the PFD-TA PLL consumes 5 mW from a 1.1 V supply.INDEX TERMS Time amplifier (TA), digitally controlled oscillator (DCO), digital phase-locked loop (PLL), PLL jitter analysis, reference spur, phase interpolator (PI) nonlinearity calibration.

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Section: B Optimum Proportional Path Gainmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

et al. 2022

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“…Equation (21) becomes the same as (20) for K Q > 3 and n p = 2 NDTC . In fact, for a fair comparison, we assume equal number of quantization levels of the DTC for both the systems.…”

Section: Spectrum Of Dfcs Versus Dpcsmentioning

confidence: 99%

“…Fig. 11: Comparison of the maximum spurs in dBc, in a DFC (from (20)) and in a DPC (from (21) In a DPC, by changing the input word p, with q fixed, the periodicity 2K Q of the quantization sequence is fixed, and therefore so are the number of subharmonics. In other words, for a fixed q, the set of subharmonics is always the same, while p changes only their position in the spectrum.…”

Section: Spectrum Of Dfcs Versus Dpcsmentioning

confidence: 99%

Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR

Palattella

Klumperink

Alink

et al. 2019

IEEE Trans. Circuits Syst. I

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In this paper we propose and analyze a Pulse-Output Digital-to-Frequency Converter (DFC) generating square waves, that uses a Digital-to-Time Converter (DTC) to correct the spurious tones (spurs) in the output spectrum. We focus on high-level architectural potential, discuss the design features of a DTC suitable for the proposed system and we explore possibilities and limits of this approach in terms of cleanness of the output spectrum. Behavioral model simulations confirm the theoretical analysis presented. Besides an analytical description of the output spurs, we derive a closed-form estimate of the worstcase spur, that leads to a simple design equation. This is useful to determine the DTC requirements (number of bits, Integral Non-Linearity (INL)) given a certain Spurious-Free Dynamic Range (SFDR) target. We show that the maximum spur strength, in dBc, depends exclusively on the ratio between the output frequency and the clock frequency and the DTC features (number of bits, INL and other impairments) and increases with the ratio by 6 dB per octave.

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“…Thus, frequency synthesizers are often benchmarked in terms of maximum spur, e.g. fractional-N PLLs [87][88][89].…”

Section: Pulse-output Dfcs: Reducing Spurs With a Dtc 41 Introductionmentioning

confidence: 99%

Digital-to-Time Converters for spur correction in Digital Frequency Synthesis

Palattella¹

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24.8 A 14nm fractional-N digital PLL with 0.14ps<inf>rms</inf> jitter and −78dBc fractional spur for cellular RFICs

Cited by 10 publications

References 6 publications

A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR

Digital-to-Time Converters for spur correction in Digital Frequency Synthesis

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