24-Gb/s Input-Data-Independent Clock and Data Recovery Utilizing Bit-Efficient Braid Clock Signaling With Fixed Embedded Transition for 8K-UHD Intrapanel Interface

Time jitter analysis is an important means to evaluate the performance of a high‐speed serial communication system. Clock data recovery (CDR) is a critical component of a high‐speed serial link that recovers the reference clock from a signal for jitter analysis. Traditional studies focused on CDR technology for the non‐return‐to‐zero pattern based on a hardware design, but little work has been devoted to the software CDR especially for the four‐level pulse amplitude modulated (PAM4) encoded data signals. This study proposes a new software algorithm to recover clocks from PAM4 signals that is capable of extracting synchronous clocks from PAM4 signals to design an ideal software phase‐locked loop for clock recovery. The proposed algorithm extracts more types of data transition edges than hardware methods to avoid the loss of jitter information. Besides, the algorithm designs an ideal phase‐locked loop to improve the filtering accuracy. This algorithm has been implemented in MATLAB, and shows superior performance to that of conventional CDR technology.

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A software PAM4 clock data recovery algorithm for high‐speed serial communication

Song

Chen

et al. 2022

IET Communications

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A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances

Sim,

Park

et al. 2024

IEEE J. Solid-State Circuits

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A 5–13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process

Shu

Huang

et al. 2020

IEEE Trans. Circuits Syst. I

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24-Gb/s Input-Data-Independent Clock and Data Recovery Utilizing Bit-Efficient Braid Clock Signaling With Fixed Embedded Transition for 8K-UHD Intrapanel Interface

Cited by 7 publications

References 9 publications

A software PAM4 clock data recovery algorithm for high‐speed serial communication

A software PAM4 clock data recovery algorithm for high‐speed serial communication

A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances

A 5–13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process

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