28nm FDSOI CMOS Technology (FEOL and BEOL) Thermal Stability for 3D Sequential Integration: Yield and Reliability Analysis

Cavalcante, Charles Esteffan; Fenouillet-Beranzer, C.; Batude, P.; Garros, X.; Federspiel, X.; Lacord, J.; Kerdilès, S.; Royet, A.S.; Acosta-Alba, P.; Rozeau, O.; Barral, V.; Arnaud, F.; Planes, N.; Sassoulas, Pierre-Olivier; Ghegin, E.; Beneyton, R.; Gregoire, M.; Weber, O.; Guérin, C.; Arnaud, L.; Moreau, S.; Kies, R.; Romano, G.; Rambal, N.; Magalhães, Ana Carolina de; Ghibaudo, G.; Colinag, J-P.; Vinet, M.; Andrieu, F.

doi:10.1109/vlsitechnology18217.2020.9265075

Cited by 19 publications

(18 citation statements)

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“…INTRODUCTIONowadays, to further explore alternative scaling paths, monolithically stacked devices are emerging [1-8]. However, vertical stacking of multiple functional layers brings severe limitation of the thermal budget applicable to top-tier devices (e.g., 500 °C for 2 h [3,6]), because bottom-tier ones must preserve their functions and performances during subsequent thermal processing steps. One of the most critical challenges is the formation of junctions on the top layers (e.g., source and drain [9] and their extension [8] for metal-oxidesemiconductor field-effect transistors (MOSFET), back-surface…”

mentioning

confidence: 99%

Solid Phase Recrystallization in Arsenic Ion-Implanted Silicon-On-Insulator by Microsecond UV Laser Annealing

Tabata

Rozé

Acosta-Alba

et al. 2022

IEEE J. Electron Devices Soc.

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UV laser annealing (UV-LA) enables surfacelocalized high-temperature thermal processing to form abrupt junctions in emerging monolithically stacked devices, where the applicable thermal budget is restricted. In this work, UV-LA is performed to regrow a silicon-oninsulator wafer partially amorphized by arsenic ion implantation as well as to activate the dopants. In a microsecond scale (~10 -6 s to ~10 -5 s) UV-LA process, monocrystalline solid phase recrystallization and dopant activation without junction deepening are evidenced, thus opening various applications in low thermal budget integration flows. However, some concerns remain. First, the surface morphology is degraded after the regrowth, possibly because of the non-perfect uniformity of the used laser beam and/or the formation of defects near the surface involving the excess dopants. Second, many of the dopants are inactive and seem to form deep levels in the Si band gap, suggesting a further optimization of the ion implantation condition to manage the initial crystal damage and the heating profile to better accommodate the dopants into the substitutional sites. Index Terms-laser annealing, solid phase recrystallization, silicon-on-insulator I. INTRODUCTIONowadays, to further explore alternative scaling paths, monolithically stacked devices are emerging [1-8]. However, vertical stacking of multiple functional layers brings severe limitation of the thermal budget applicable to top-tier devices (e.g., 500 °C for 2 h [3,6]), because bottom-tier ones must preserve their functions and performances during subsequent thermal processing steps. One of the most critical challenges is the formation of junctions on the top layers (e.g., source and drain [9] and their extension [8] for metal-oxidesemiconductor field-effect transistors (MOSFET), back-surface

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mentioning

confidence: 99%

Solid Phase Recrystallization in Arsenic Ion-Implanted Silicon-On-Insulator by Microsecond UV Laser Annealing

Tabata

Rozé

Acosta-Alba

et al. 2022

IEEE J. Electron Devices Soc.

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“…In the conventional process, sidewalls are manufactured by depositing SiN x via ALD at 600 ˚C. If the temperature of the sidewall formation process is directly reduced to 500 ˚C, then the reliability of the SiN x film will degrade, where the etching rate in the HF solution will be increased twice in contrast to that fabricated at a conventional high-temperature process [111] .…”

Section: Process Schemes For Integrated Devicesmentioning

confidence: 99%

Advanced process and electron device technology

Zhang¹,

Su²,

Chang³

et al. 2022

Tsinghua Sci. Technol.

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This article reviews advanced process and electron device technology of integrated circuits, including recent featuring progress and potential solutions for future development. In 5 years, for pushing the performance of fin field-effect transistors (FinFET) to its limitations, several processes and device boosters are provided. Then, the three-dimensional (3D) integration schemes with alternative materials and device architectures will pave paths for future technology evolution. Finally, it could be concluded that Moore's law will undoubtedly continue in the next 15 years.

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“…Most studies on doped HfO2 films adopted high rapid thermal annealing (RTA) above 500 °C, to acquire a large remanent polarization (2Pr > 40 µC/cm 2 ) [4][5][6]. However, a high thermal budget affects the transistor performance and back-end-of-line (BEOL) reliability when the capacitors are integrated into the state-of-the-art CMOS manufacturing processes [7], whereas a higher crystallization anneal temperature contributes to higher remanent polarization for high density memory application with thinner capacitors. To date, MFM capacitors comprising TiN/HZO/TiN have been incorporated in the BEOL process by applying a temperature of < 450 °C to avoid the degradation of the metal layers, thus demonstrating the functionality of the 1T1C FeRAM array with no degradation of the CMOS characteristics [8].…”

Section: Introductionmentioning

confidence: 99%