2D fin field-effect transistors integrated with epitaxial high-k gate oxide

p-Type High-Performance WSi2N4 MOSFETs with the Ultrashort Scale of Sub-5 nm

“…Experimental and theoretical studies have shown that the use of high -k dielectric layers can suppress leakage currents, which in turn improves the transport properties of FETs. ,, Here, the I–V g curves of sub-5 nm p- and n- type WSi 2 N 4 MOSFETs without underlap region are investigated using HfO 2 (ε = 25) as the gate dielectric layer in Figure S2. Compared with the case of SiO 2 (ε = 3.9) dielectric layer, the use of high -k dielectric layer can significantly enhance the electrostatic gate control capability of the device, regardless of the p- or n- type WSi 2 N 4 MOSFETs.…”

Two‐Dimensional Semiconductors: From Device Processing to Circuit Integration

“…The processes flow chart ( Figure a) clearly illustrate the similarities and differences between the semiconductor manufacturing process and the 2DM‐based processes. Planar double gate transistors (Figure 6b) [ 93 ] and fin field‐effect‐transistor (FinFET) (Figure 6c) [ 94 ] based on 2DMs have been prepared, partially drawing on the planar (Figure 6d) [ 95 ] and FinFET (Figure 6e) [ 2a,96 ] structures of Si transistors. Si wafer can be obtained directly from the factory and prepared into transistor structures based on subsequent processes, while 2DM wafers must form continuous and dense thin films on specific wafers, and the related growth methods have been mentioned in the previous section where the material itself serves as a channel layer.…”

“…Reproduced with permission. [ 94 ] Copyright 2023, Springer Nature. d) TEM cross‐section image of Si transistor.…”

“…Reproduced with permission. [ 94 ] Copyright 2023, Springer Nature. 2DM GAAFET's schematic of c) device structure and d) process flow.…”

Polarized Tunneling Transistor for Ultralow-Energy-Consumption Artificial Synapse toward Neuromorphic Computing

“…Recently, a burgeoning interest in three-terminal devices for artificial synapses has been observed, largely due to their nondestructive weight-update function, which benefits from the separation of writing (gate) and reading (drain) terminals. ,− The weight updates in these devices are governed by various charge-storage mechanisms, including interfacial traps, , floating gates, − ion intercalation, , and defects in dielectrics. , Additionally, three-terminal devices featuring charge-storage capabilities have been rigorously explored in the context of van der Waals heterostructures. These structures are composed of two-dimensional (2D) materials exhibiting distinct structural and material properties, − and have shown potential for nonvolatile electronic and optoelectronic memory applications. ,,− Notably, Large-scale MoS 2 floating-gate transistor arrays have been successfully fabricated, and the subsequent integration of these arrays into circuits has enabled the realization of logic-in-memory functionality, further highlighting the commercial prospects of three-terminal devices employing 2D materials. , However, these devices have not yet proven suitable for low-energy-consumption artificial synapse applications due to their limited operation speed. Although the floating gate configurationfeaturing uniform atomically sharp interfaces and a high gate coupling ratiocan address this issue, concerns regarding the complex fabrication processes remain. , As a result, it is crucial to meticulously design an alternative memory structure that can provide a viable solution to the low operation speed challenge.…”