3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS

Norimatsu, Takayasu; Kimura, Takashi; Kogo, Kenji; Kohmu, Naohiro; Yuki, Fumio; Nakajima, Noriaki; Muto, Takashi; Nasu, Junya; Komori, Takemasa; Koba, Hideki; Usugi, Tatsunori; Hokari, Tomofumi; Kawamata, Tsuneo; Itō, Yūichi; Umai, Seiichi; Tsuge, M.; Yamashita, T.; Hasegawa, Michiko; Higeta, K.

doi:10.1109/isscc.2016.7417906

Cited by 32 publications

(5 citation statements)

References 2 publications

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“…However, the interconnect partially takes advantage of the technology scaling, because faster transistors enable a better circuit to overcome the increased channel loss. Figure 11A shows a survey from the state-of-the-art published works ( Tamura et al, 2001 ; Haycock & Mooney, 2001 ; Tanaka et al, 2002 ; Lee et al, 2003 , 2004 ; Krishna et al, 2005 ; Landman et al, 2005 ; Casper et al, 2006 ; Palermo, Emami-Neyestanak & Horowitz, 2008 ; Kim et al, 2008 ; Lee, Chen & Wang, 2008 ; Amamiya et al, 2009 ; Chen et al, 2011 ; Takemoto et al, 2012 ; Raghavan et al, 2013 ; Navid et al, 2014 ; Zhang et al, 2015 ; Upadhyaya et al, 2015 ; Norimatsu et al, 2016 ; Gopalakrishnan et al, 2016 ; Shibasaki et al, 2016 ; Peng et al, 2017 ; Han et al, 2017 ; Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ), where we can confirm the correlation between the technology node and the data rate. On the other hand, however, overcoming the increased channel loss has become more and more expensive as the loss is going worse as the bandwidth increases; the equalization circuits consume too much power to compensate the loss, which makes people hesitant to increase the bandwidth.…”

Section: Interconnectmentioning

confidence: 99%

Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing their limits, and therefore are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a large challenge for computer hardware industry. However, at the same time it also provides great opportunities for the hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today’s computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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Section: Interconnectmentioning

confidence: 99%

Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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“…The proliferation of copper-based links in this area can be mainly attributed to the advancements of CMOS technologies and circuit techniques. By utilizing advanced CMOS technologies and equalization techniques, operations at higher than 25 Gb/s even in severe loss conditions of more than 40 dB were achieved [ 9 , 10 , 11 ]. Recently, circuit designers attempt to overcome the limitations of copper by introducing a pulse-amplitude-modulation (PAM) signaling that can enhance the effective data rate for the same loss condition as the conventional binary signaling [ 12 , 13 , 14 , 15 ].…”

Section: Silicon Photonics For High-speed Data Communicationsmentioning

confidence: 99%

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

Jeong

Bae

Jeong

2017

Sensors

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The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

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“…Comparators, used as samplers or slicers in decision feedback equalisers (DFEs), face the challenge of sensing signals at data rates above 20 Gb/s with limited input signal swing. Considering the aggregated losses of low-pass channels, which can reach up to 40 dB, signal amplitude at comparator input could be as low as 20 mV [1]. As a result, comparator sensitivity specifications become limited by the accuracy of the offset correction scheme.…”

Section: Introductionmentioning

confidence: 99%

A digital phase‐based on‐fly offset compensation method for decision feedback equalisers

Amaya

Ardila

Roa

2021

IET Circuits, Devices & Syst

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A low-complexity method to reduce the offset voltage of dynamic comparators employed as samplers in decision feedback equalisers (DFE) is introduced. The authors propose the phase-domain offset reduction technique (PORT), which leverages an all-digital phase estimation of output data for offset compensation, without setting the comparator input to a common-mode voltage (V CM). While traditional techniques might break the data link for offset adjustment, the proposed technique allows calibrating the comparator on-thefly. Measurements from a 26-dB-loss on-chip emulated channel with chip-scope capability validates PORT through eye-diagrams at sampler input. A prototype was implemented in a TSMC 130 nm 1.2 V process, and experimental results show the possibility of extending PORT to state-of-the-art technology nodes for multi-gigabit operation. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS

Cited by 32 publications

References 2 publications

Today’s computing challenges: opportunities for computer hardware design

Today’s computing challenges: opportunities for computer hardware design

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

A digital phase‐based on‐fly offset compensation method for decision feedback equalisers

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