3-D ICs: Motivation, performance analysis, technology and applications

Abstract

Interconnect delays, bandwidth and power consumption are increasingly dominating IC performance due to increases in chip size and reduction in the minimum feature size, in spite of new materials like Cu with low-k dielectric. Thereby severely limiting chip performance unless a paradigm shift from present interconnect architecture is introduced. One such promising technique is three-dimensional (3-D) ICs with multiple active Si layers and vertical interconnects. This paper presents a comprehensive review of 3-D ICs with multiple semiconductor layers. It is shown that significant improvement in performance and reduction in wire-limited chip area can be achieved with 3-D ICs if some long horizontal interconnects can be replaced by short vertical inter-layer interconnects. We also address the thermal concerns due to increased power density for 3-D circuits. Finally, an overview of some of the processing techniques which can be used to fabricate these circuits, is reviewed.

3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers

“…The adhesion of SOG material is also a critical issue [6]. Moreover, the low conductivity of the isolation layer introduces a heat accumulation issue [11] [13]. Thus, a 3D memory design excluding an isolation process can significantly benefit from lower fabrication cost and process complexity.…”

3D integration: Advantages, enabling technologies & applications

“…Thus 3D integration alleviates the interconnect related challenges such as delay and power dissipation, and can also facilitate integration of heterogeneous technologies all in a smaller form factor. With more than Moore focusing on functional diversification, heterogeneous integration provides a cost effective path for stacking of different technologies separately fabricated with different materials and processes [6,7] While 3D integration offers a path for higher performance, higher density, higher functionality, and smaller form factor; getting there requires new and improved enabling technologies and integration schemes. The enabling technologies include Through Silicon Vias (TSV), bonding and thinning.…”

Cell transformations and physical design techniques for 3D monolithic integrated circuits

“…3D integration provides an effective platform for realizing future gigascale circuits by integrating multiple layers of active devices vertically [Saraswat 2010;Pavlidis and Friedman 2009]. 3D fabrication technologies can be broadly classified into two groups according to the used integration scheme: (a) 3D parallel integration (or ThroughSilicon Via, TSV, -based technology) in which each active layer, along with its respective interconnect metal layers, is fabricated separately and is subsequently stacked via TSVs [Koester et al 2008;Sillon et al 2008] Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation.…”