3D integration: Advantages, enabling technologies &amp;amp; applications

Sadaka, Mariam; Radu, Ionut; Cioccio, L. Di

doi:10.1109/icicdt.2010.5510283

Cited by 17 publications

(9 citation statements)

References 10 publications

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“…Its main purpose is to establish electrical connectivity between devices in two different dies in a 3D-IC stack. There is presently no consensus on the most efficient bonding technique which largely depends on the application requirements [30,32,33]. There are various bonding techniques [34] which range from direct oxide bonding, metal to metal (Cu-Cu) bonding, with different variants and adhesives.…”

Section: Vertical Interconnect Technology Development (Tsv)mentioning

confidence: 99%

Three-Dimensional Integration: A More Than Moore Technology

Pangracious

Marrakchi²,

Mehrez

2015

Lecture Notes in Electrical Engineering

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Three-dimensional integrated circuits (3D-ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals and offer a promising solution for reducing both silicon footprint and interconnect length without shrinking the transistors. However, before these advantages can be realized, key technology and CAD challenges of 3D-ICs must be addressed. More specifically, the process required to build circuits with multiple layers of active devices and CAD tools used for design and validation of such circuits. Several such methodologies and CAD tools associated with the design fabrication of 3-D ICs are discussed in this chapter. Few successful 3D-IC design methods and CAD tools and benefits of applying 3D design to the future reconfigurable systems are also discussed in this chapter. IntroductionThe ongoing demand for greater functionality resulting in multiple IC products, longer off-chip interconnects ravage the performance of microelectronic systems. The advent of System-on-Chip (SoC) in the mid 1990s primarily addressed the increasing delay of the off-chip interconnects. Integrating all of the components on a monolithic substrate enhances the overall speed of the system, while decreasing the power consumption. To assimilate disparate technologies, however several difficulties must be surmounted to achieve high yield for the entire system. Additional system requirements for the radio frequency (RF) circuitry, passive elements, and discrete components, such us decoupling capacitors, which are not easily integrated due to performance degradation or size limitations. While Moore's law [1] and the pursuit of ever increasing transistor counts is well known in IC design and manufacturing circles, what is seldom brought to light for others, are the escalating cost and technology challenges associated with this pursuit. Smaller transistors and larger dies have been reasonable answer to this quest in the past. Stacked dies using wire bond connections and flip-chips have even been employed to create system-in-package (SiP) solutions that meet the needs of some. Looking for alternative solutions for next generation designs, that meet the performance, integration, form-factor, manufacturability, and cost requirements, may have begun to look at going up rather than out. With this trend, the Three-dimensional (3D) integration using through-silicon via (TSV) technology has gained much attention. Once the domain of specialist applications, more mainstream users, such as memories, microprocessors ans specialized logic designs are now being considered as TSV candidates. The advantages of 3D-IC integration are better electrical performance, low power consumption, lower area and weight and high performance (Fig. 2.1). Opportunities for Three-Dimensional IntegrationPerformance requirements such as increased band...

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Section: Vertical Interconnect Technology Development (Tsv)mentioning

confidence: 99%

Three-Dimensional Integration: A More Than Moore Technology

Pangracious

Marrakchi²,

Mehrez

2015

Lecture Notes in Electrical Engineering

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“…While significant R and D efforts have been expended on various planar approaches, 3DIC integration technologies are undoubtedly gaining momentum as potential pioneers in the challenge to meet the demands of the form factor, performance, and cost through this decade and beyond [3,11]. This study conducted expert interviews after reviewing the relevant literature to identify the four alternative 3DIC integration technologies-3DIC packaging, 3DIC through-silicon via (3DIC TSV), 3D silicon TSV (3D Si TSV), and 2.5D through-silicon interposer (2.5D TSI)-that are mostly the concern of the Taiwanese semiconductor industry.…”

Section: Perspectives On 3dic Integration Technologiesmentioning

confidence: 99%

“…The 3DIC packaging technologies exploit a z-axis dimension to provide a volumetric packaging solution for higher integration and performance, as well as to save space by stacking either separate chips or separate packages in a single package [11]. The two types of 3DIC packaging technologies are coined as "die stacking" or "package stacking" technologies [12].…”

Section: Dic Packagingmentioning

confidence: 99%

Technology Evaluation and Selection of 3DIC Integration Using a Three-Stage Fuzzy MCDM

Lee

Chou

2016

Sustainability

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Abstract:For the purpose of the sustainable development in the global semiconductor industry, emerging three-dimensional integrated circuit (3DIC) integration technologies have demonstrated their importance as potential candidates for extending the lifespan of Moore's Law. This study aimed to explore a technology selection process involving a three-stage fuzzy multicriteria decision-making (MCDM) approach to facilitate the effective assessment of emerging 3DIC integration technologies. The fuzzy Delphi method was first used to determine the important criteria. The fuzzy analytic hierarchy process (fuzzy AHP) was then adopted to derive the weights of the criteria. The fuzzy technique for order of preference by similarity to ideal solution (fuzzy TOPSIS) was finally deployed to rate the alternatives. Empirical results indicate that market potential, time-to-market, and heterogeneous integration are the top three decision criteria for the selection of 3DIC integration technologies. Furthermore, 2.5D through-silicon interposer (TSI) is of primary interest to the Taiwanese semiconductor industry, followed by 3DIC through-silicon via (TSV), 3D packaging, and 3D silicon TSV (Si TSV). The proposed three-stage fuzzy decision model may potentially assist industry practitioners and government policy-makers in directing research and development investments and allocating resources more strategically.

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“…It is important to note that 3D stacking generally encompasses both silicon level stacking and packaging level stacking. Reviews of the various types of 3D stacking, and their advantages, may be found in recent publications [4][5][6][7][8][9].…”

Section: Current Statusmentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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3D integration: Advantages, enabling technologies & applications

Cited by 17 publications

References 10 publications

Three-Dimensional Integration: A More Than Moore Technology

Three-Dimensional Integration: A More Than Moore Technology

Technology Evaluation and Selection of 3DIC Integration Using a Three-Stage Fuzzy MCDM

3D integration review

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