3D integration review

Abstract

3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

Multiwavelength Raman characterization of silicon stress near through-silicon vias and its inline monitoring applications

“…[5][6][7][8][9][10] There have been many encouraging technical breakthroughs toward the industrial implementation of TSV technology in volume production. 5-10 Yet, we are constantly uncovering new problems and striving to find the solutions to the new challenges.…”

“…[5][6][7] Copper (Cu), tungsten (W), and poly silicon (Si) have been chosen as filler conducting materials depending on the final product's application and integration strategy. [5][6][7][8][9][10] One of the main concerns in TSV technology is stress in Si induced by the difference in the coefficients of thermal expansion (CTE) between the choice of filler materials and Si during thermal cycling in the integration process steps. [5][6][7][8][9][10][11][12] The induced stress in Si near TSVs can result in electrical performance variation of stress-sensitive devices and device reliability degradation.…”

“…[5][6][7][8][9][10] One of the main concerns in TSV technology is stress in Si induced by the difference in the coefficients of thermal expansion (CTE) between the choice of filler materials and Si during thermal cycling in the integration process steps. [5][6][7][8][9][10][11][12] The induced stress in Si near TSVs can result in electrical performance variation of stress-sensitive devices and device reliability degradation. [11][12][13][14][15] It can also cause catastrophic device failures such as wafer breakage, cohesive cracking in Si, and interfacial delamination between the TSVs and Si.…”

Analysis of encapsulation process in 3D stacked chips with different microbump array

“…Despite all the benefits in 3D system integration with TSV, as mentioned by several scholars in the literature [2][3][4], there are still many challenges ahead [5][6][7] before this technology is able to be fully implemented in electronic packages. At the moment, TSV technology is still largely limited to the areas of homogeneous system integration in DRAM, and CMOS image sensors.…”

Three Dimensional integration - Considerations for memory applications

“…Finally we will discuss some recent relevant results on 3D memory in a high performance environment. The reader is referred to a detailed review of 3D technology by Farooq and Iyer [3]. The reader is also referred to a special issue on 3Di of The IBM journal of Research and Development [4].…”