Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules.Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.

3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

I. AbstractA high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2x wiring levels, and increased 1x wire aspect ratios in lowk, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK Chip-Package Interaction (CPI) reliability, including in the most aggressive organic flipchip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria. II. BEOL IntegrationAggressive 0.7x scaling from 65nm BEOL wiring and contact dimensions has been achieved using hyper-NA (1.2NA) lithography. This enables a 2x active area reduction for migratable designs. The 45 nm BEOL hierarchy is shown in Fig. 1. At the 1x wiring levels (M1-M3), BEOL delays are largely impacted by resistance increases from scaling. Increased aspect ratio in conjunction with an optimized Cu barrier-seed process results in up to 25% resistance and 20% RC reductions, respectively, per Fig. 2. Typically, increasing Cu aspect ratios degrades stress migration (SM) and electromigration (EM) reliability. However, Figs. 3-4 show than an optimized Cu barrier-seed process and tooling enables zero SM fails and good EM performance. Thus scaling impacts to BEOL parasitics at 45 nm 1x levels are mitigated, while extending the low-k SiCOH film and integration scheme [1] from 90 and 65 nm technologies [2]. The industry-wide effort to integrate ULK BEOL dielectrics has focused primarily on the 1x wiring levels [3][4][5]. In contrast, our strategy is to introduce ULK at the 2x levels (M4-M6), which are typically dominated by relatively longer RC-dominated runs. The 15% RC benefit for ULK (k=2.4) over low-k (k=3.0) at these levels, as shown in Fig. 5, is leveraged to deliver superior BEOL performance at reduced risk. These 2x levels consist of dual damascene Cu in homogeneous PECVD ULK porous-SiCOH which is based on advanced precursors and UV-cure tooling [6][7]

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Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices.