No abstract

No abstract

In this paper, we present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm 2 , and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28nm from 45nm technology. Our high-density SRAM bit-cell (area= 0.120mm 2 ) has a demonstrated Static Noise Margin (SNM) of 213mV at 1V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28nm LP poly/SiON reference [3]. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT~2mV.um) versus our previously-reported result [2]. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k~2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.

No abstract

This letter presents evidence of an oxidation-driven failure mechanism in Cu interconnects integrated with ultralow-κ materials. It is found that the open pore structure of ultralow-κ materials allows oxidants in the ambient to reach the interconnect structure and induce oxidation of Cu. In contrast to a normal oxidation process where Cu is in contact with the oxidant, oxidation is controlled by the outdiffusion of Cu through the barrier layers, Ta and SiCN, to form Cu oxide in the pores of the dielectric material. The loss of Cu by outdiffusion induces extensive voiding and subsequent failure in Cu interconnects.