3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

“…• According to the core material: silicon (today), organic (currently considered), or glass substrates (future) [16], [52], [53] • According to the interposer type: fully passive, with embedded components such as microfluidic channels [54], or with active components [8], [20], [21], [55] • According to the mounting approach: one-sided or doublesided die placement, distributed high-power or low-power die allocation [8] • According to the chip design: prefabricated dies stacked onto the interposer (such as the AMD Fiji/Fury GPU with stacked HBM chips [56], [57], [58]) or custom dies designed for specific applications (such as the Xilinx Virtex-7 FPGA [59]) As of today, there are several products with interposer technology available on market, notably the AMD Fiji/Fury GPU [56], [57], [58] and the Xilinx Virtex-7 FPGA [59]. In 2016, CEA Leti demonstrated their second generation 3D-NoC technology [20], [21], which combines a series of small dies ("chiplets") fabricated at the FDSOI 28 nm node and co-integrated on a 65 nm CMOS interposer.…”

Heterogeneous 2.5D integration on through silicon interposer

“…Without compromising processing speed, the integration of multi-chips in one interposer on the package tends to generate higher heat density, which needs to be addressed in the 2.5D or 3D package design. [102][103][104][105][106][107][108][109][110][111][112][113][114][115] A schematic of the cooling concepts is illustrated in Figure 50.…”

“…Recent research is conducted on the thermal management of two stacked chips on Si carriers cooled by microchannel heat sinks fabricated in the chip carriers. 107,108 A heat flux of 100 W/cm 2 can be dissipated from each chip stack through dual in-port fluidic design.…”

Evaluation of Si liquid cooling structure with microchannel and TSV for 3D application

“…Recently, several studies of microchannel liquid cooling at a chip level have been introduced (Colgan et al 2005;Khan et al 2013;Bakir et al 2008). In terms of cooling capability, direct liquid cooling at the chip level has been found to be significantly more effective than any indirect liquid cooling at the package level.…”