3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

Civale, Yann; Tezcan, Deniz Sabuncuoglu; Philipsen, Harold; Duval, Fabrice; Jaenen, Patrick; Travaly, Youssef; Soussan, Philippe; Swinnen, Bart; Beyne, Eric

doi:10.1109/tcpmt.2011.2125791

Cited by 50 publications

(14 citation statements)

References 15 publications

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“…The elastic moduli of polymers are normally on the order of several GPa at room temperature, ∼10% of commonly used SiO 2 -liner 70 GPa, and thus are effective in reducing thermal stresses due to the relatively large deformation while experiencing thermal stress [43]- [50]. In addition, the low relative dielectric constants of polymers are also beneficial to achieving low TSV capacitance [41]. Among the polymers, benzocyclobutene (BCB) is a suitable polymer for liner applications due to its low elastic modulus (2.9 GPa), good chemical and thermal stability, low dielectric constant (∼3), and low outgassing.…”

Section: -D Integration Is Emerging As a Promising Technologymentioning

confidence: 99%

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

Huang

Pan

Liu

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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Through-silicon vias (TSVs) using benzocyclobutene (BCB)-liners as the insulator have the potential for reducing the TSV capacitances and the thermal expansion stresses. This paper reports the assessments of BCB-liner TSVs with respect to thermal and electrical properties. The C-V and I-V characteristics are measured at room temperature and at an elevated temperature as high as 125°C to characterize the electrical properties of capacitance and leakage current at different temperatures. Some C-V and I-V features associated with BCB-liners are discussed and the mechanisms are analyzed. Thermal cycling between −65°C and 150°C is performed, and the C-V and I-V characteristics are measured before and after thermal cycling to evaluate the thermomechanical stability of the BCB-liners, and the results show that the C-V and I-V properties are improved after thermal cycling. These preliminary results on the electrical and thermal properties of BCB-liner TSVs show that they have good thermal stability.

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Section: -D Integration Is Emerging As a Promising Technologymentioning

confidence: 99%

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

Huang

Pan

Liu

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…Following the etching process, the via sidewalls are passivated by parylene deposition. The use of polymer liner for TSV passivation has been previously demonstrated [7], [26], [27]. In conventional techniques, the deposited dielectric layer on the landing pad has to be etched.…”

Section: B Photolithography and Post-processingmentioning

confidence: 99%

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Temiz

Guiducci

Leblebici

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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Abstract-This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple alternative to spincoated resist. Unlike conventional photolithography methods, the technique allows resist patterning on very high topography, and therefore chip-level photolithography can be done without using any wafer reconstitution approach. Moreover, this paper proposes a via sidewall passivation method which eliminates dielectric etching at the bottom of the via and simplifies the whole integration process. In this paper, two 50-μm-thick chips were post-processed, aligned, bonded, and connected by Cu TSVs, which have parylene sidewall passivation. Daisy-chain resistance measurements show 0.5-resistance on average for 60-μm-diameter TSVs, with a yield of more than 99% for 1280 TSVs from five different chip stacks. Subsequently, the techniques were applied to CMOS microprocessor stacking as a test vehicle. Die-level post-CMOS processing for 40-μm-diameter via etching, redistribution layer patterning, and chip-to-chip bonding were successfully demonstrated with the real chips.Index Terms-3-D integration, die-level processing, dry-film lithography, parylene bonding, post-complementary metal oxide semiconductor (CMOS) processing, through-silicon via (TSV), via-last TSV.

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“…Polymer materials, in consideration of the outstanding performance in the low crosstalk, capacitance and inductance [3][4], are the selective insulated materials that can be applied in the CIS-TSV packaging sidewall insulation coating process[5] [6]. The spray nozzle atomizes the polymer solution to liquid drops with ultrasonic oscillation [7].…”

Section: Introductionmentioning

confidence: 99%

Novel spray coating process with polymer material applied in CIS wafer-level-packaging

Zhuang

Dai

Niu

et al. 2014

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)

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This paper studies a creative spray coating process applied to the forming of sidewall insulation of through silicon via (TSV) in CMOS image sensor (CIS) packaging. In this paper, through controlling the nitrogen gas pressure, rate of polymer solution flow and plate temperature, we present a lowtemperature-first and high-temperature-last spray coating method. Using this novel spray coating process, one kind of phenolic aldehyde polymer is deposited on the sidewall of though silicon via with the diameter of 65μm and depth of 120μm. To promote the performance of TSV sidewall insulation and electrical interconnection characteristic, the thickness of polymer on the sidewall was aimed to not less than 2μm. The temperature of spray coating process was adjusted to control the viscosity of polymer to achieve the insulation layer thickness target value. Finally, we fabricate the adequate polymer insulation layers in the certain aspect ratio (2:1) TSV structure successfully. IntroductionIn the CIS-TSV packaging, the efforts of process are focused on increasing the resolution of image sensors and miniaturization in pixel sizes for electric products like mobile phones and laptops. The key technology for wafer level packaging of CIS is Through Silicon Via, TSV technology is one kind of rising interconnecting technology applied in the high density 3-D packaging[1]. 3-D interconnection technology needs to implement one side to the other side of the electrical interconnection in semiconductor device wafers. For this reason, redistribution layer is allowed on the backside of the wafer through TSV packaging process [2].In these key TSV processes, the Si etching process is followed by the via insulation coating. Polymer materials, in consideration of the outstanding performance in the low crosstalk, capacitance and inductance [3][4], are the selective insulated materials that can be applied in the CIS-TSV packaging sidewall insulation coating process[5] [6]. The spray nozzle atomizes the polymer solution to liquid drops with ultrasonic oscillation [7]. The nitrogen gas transports these liquid drops to the surface of wafer for forming the polymer coating as shown in Fig. 1 under the certain gas pressure [8]. By the spraying and flowing characters of polymer solution drops on the sidewalls of TSV, the polymer forms the insulation layers on the sidewall of TSV and surfaces of wafers after the solvent evaporates. The greatest challenge to realize the polymer insulation spray process is the uniformity and void-free on the sidewall of each TSV. Meanwhile, the scallop caused by deep reactive ion etching (DRIE) can deteriorate the uniformity of polymer sidewall insulation layer of TSV.

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3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

Cited by 50 publications

References 15 publications

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Novel spray coating process with polymer material applied in CIS wafer-level-packaging

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