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The results of a wet alkaline seed deposition process directly on a thin adhesion promoter film, such as chemical vapor deposition ͑CVD͒ Co, are presented. This solution has been successfully used for copper plating on blanket and patterned through-silicon-via ͑TSVs͒ wafers covered with either silicon oxide/physical vapor deposition ͑PVD͒ Ta/CVD Co or silicon oxide/PVD Ti/CVD Co stacks. Such direct plated films were used as seed layers for subsequent copper plating from an in-house-made acidic Cu bath with model additives poly͑ethylene glycol͒ ͑PEG͒, bis͑3-sulfopropyl͒ disulfide ͑SPS͒, and Janus Green B ͑JGB͒. We report the impact of the directly plated stack composition and thicknesses on the integration of the wet alkaline seed in TSVs with 5 m width and high aspect ratio ͑HAR͒ as high as 8:1. The conformal wet seed layer enables the achievement of a successful void-free filling using an in-house made acidic Cu bath with model additives ͑SPS, PEG, and JGB͒.

Bath stability monitoring of electroless copper deposition has been done with different methods. A combination of UV-VIS spectra and pH measurement enabled us to determine the degradation of an electroless Cu solution. The pH of the Cu-containing solution gradually decreased as a function of time, while the UV-VIS absorbance increased. The decrease of pH is due to the consumption of OH − by the deposition reaction and the Cannizzaro reaction of glyoxilic acid. As application of these methods, the effect of the preparation sequence and bath stability was evaluated, bath break down was detected by the different methods used, and the potential for process monitoring was demonstrated. Furthermore, pH control during deposition was found to be very important to avoid defects in the electroless deposited seed layer, close to the via opening and top surface.

AbstractsThis work provides for the first time an experimental assessment of the impact of thermo-mechanically induced stresses by copper through-silicon vias, TSVs, on fully depleted Bulk FinFET devices. Both n and p type FinFETs are significantly affected by TSV proximity, exhibiting lower impact on drive current with respect to the planar devices. The obtained results are in agreement with the thermo-mechanical models for Cu-TSV and are supported by the 4 point bending stress calibration. Fig. 1: Cross sections of a through silicon via and a FinFET device at close proximity (a, b). The FinFET device has 40nm fin height, 20nm fin width, 1nm chemical oxide, followed by atomic layer deposition of 1.8nm HfO2 insulator and 5nm TiN work function metal gate (c,d)

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