30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current

Anghel, Costin; Hraziia,; Gupta, Ashok; Amara, Ayed Ben; Vladimirescu, Andrei

doi:10.1109/ted.2011.2128320

Cited by 129 publications

(43 citation statements)

References 20 publications

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“…1, here source is degenerately doped with boron concentration of 10 20 atoms=cm 3 and the drain is doped with phosphorus concentration of 5 Â 10 18 atoms=cm 3 are heavily doped while channel is near intrinsic with boron doping of 10 17 atoms=cm 3 [9,12,13]. Here channel is ptype doped, same as given in reference [13], because if we make it lightly n-type doped then it will cause the channel region energy band diagrams to pull downwards in Fig. 2a, hence even at V gs ¼ 0 V, tunneling of electrons will take place at sourcechannel junction that will cause to increase the OFF state TFET current.…”

Section: Working Principle Of Tfetmentioning

confidence: 99%

Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field

Yadav

Bulusu

Dasgupta

2013

Microelectronics Journal

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Section: Working Principle Of Tfetmentioning

confidence: 99%

Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field

Yadav

Bulusu

Dasgupta

2013

Microelectronics Journal

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“…But the drive current (I ON ) produced by TFET devices are not sufficient enough for fast switching. The major limitation appeared with low ON current is ambipolarity of tunnel FETs [3,4].…”

Section: Introductionmentioning

confidence: 99%

Ambipolar Reduction Methodology for SOI Tunnel FETs in Low Power Applications: A Performance Report

Dutta*,

Paitya,

Majumdar

2020

IJRTE

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 Abstract: Continuous device scaling of tunnel field effect transistors (TFET) faces real challenges in low power VLSI applications. Here in this article, the major limitation of TFET i.e. Ambipolar conduction behavior has been thoroughly discussed and remedies to suppress the leakage current (I OFF ) has also been investigated. A thin pocket layers is incorporated in source and drain regions separately at Silicon on Insulator (SOI) TFET, keeping supply voltage (V DD ) at 0.5 V. The detail analytical modeling of surface potential distribution along the channel, electric field and tunneling current is derived in this paper. Using two-dimensional numerical device simulator, the various designs are modeled and validated with our proposed methodology. Non-local Band-to-Band tunneling (BTBT) is used for simulation purpose. It is observed that a drain pocket actually helps to reduce the ambipolar conduction and provide better drive current (I ON ) for fast switching. This further improves the I ON /I OFF ratio and also results better subthreshold swing (SS) as 27.43mV/decade to optimize the device characteristics.

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“…The mechanism of conventional metal oxide semiconductor field effect transistors (MOSFETs) is thermal electron emission, so the continuous scaling of conventional MOS device is extremely difficult in nanoscale circuit because of a great many reasons, such as, VDD scaling of MOSFETs is no longer viable, OFF-state current dramatically increases and short channel effects (SCE) is severely aggravated, and a limitation of 60 mV/Dec subthreshold swing (SS) can't be broken [1,2]. In order to overcome these issues, different types of structure have been investigated in recent years, among them, tunnel field effect transistor (TFET) [3,4] is a selective candidate for future low power applications due to its complementary MOS (CMOS) process compatibility and scalability, which employs band-to-band tunneling (BTBT) mechanism and is not influenced by the short channel effect, moreover, it can break the SS limit of 60 mV/Dec, and the leakage current is small under the OFF-state condition [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate

et al. 2019

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In this paper, a dual metallic material gate heterostructure junctionless tunnel field-effect transistor (DMMG-HJLTFET) is proposed and investigated. We use the Si/SiGe heterostructure at the source/channel interface to improve the band to band tunneling (BTBT) rate, and introduce a sandwich stack (GaAs/Si/GaAs) at the drain region to suppress the OFF-state current and ambiplolar current. Simultaneously, to further decrease ambipolar current, the gate electrode is divided into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with workfunctions Φ M1 , Φ M2 and Φ M3 , respectively, where Φ M1 = Φ M3 < Φ M2 . Simulation results indicate that DMMG-HJLTFET provides superior performance in terms of logic and analog/RF as compared with other possible combinations, the ON-state current of the DMMG-HJLTFET increases up to 9.04 × 10 −6 A/µm, and the maximum g m (which determine the analog performance of devices) of DMMG-HJLTFET is 1.11 × 10 −5 S/µm at 1.0V drain-to-source voltage (Vds). Meanwhile, RF performance of devices depends on the cut-off frequency (f T ) and gain bandwidth (GBW), and DMMG-HJLTFET could achieve a maximum f T of 5.84 GHz, and a maximum GBW of 0.39 GHz, respectively.

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30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current

Cited by 129 publications

References 20 publications

Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field

Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field

Ambipolar Reduction Methodology for SOI Tunnel FETs in Low Power Applications: A Performance Report

Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate

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