300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology

Widiez, J.; Sollier, S.; Baron, T.; Martin, M.; Gaudin, G.; Mazen, F.; Madeira, F.; Favier, S.; Salaün, A.; Alcotte, Reynald; Beche, Elodie; Grampeix, H.; Veytizou, Christelle; Moulet, Jean-Sébastien

doi:10.7567/jjap.55.04eb10

Cited by 19 publications

(14 citation statements)

References 30 publications

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“…The maximum of H + implantation concentration were localized in the middle of the InP layer. Micro-cracks were observed in the InP layer after annealing at 300 • C, as seen on the SEM cross-section image [6]. These results indicate the layer transfer capability, which was confirmed during the InGaAs-OI fabrication.…”

Section: Fracture In the Inp Buffer Layersupporting

confidence: 60%

“…The crystalline defects were localized in the GaAs layer, while low crystalline defects were observed in the thin InGaAs layer, as shown on TEM image in Figure 2. values (RMS = 1.91 nm, PV = 16 nm) were low considering the large lattice mismatch between Si and InGaAs (about 8%) and our thin total buffer thickness (665 nm) [5][6][7]. To achieve splitting in the InP layer, we increased the InP layer by up to 430 nm.…”

Section: Resultsmentioning

confidence: 99%

“…The bonding interface quality of different bonding configurations (Al2O3//Al2O3, Al2O3//Si, Al2O3//SiO2, and Al2O3 under SiO2//SiO2) were studied as a function of post bonding annealing. Silicon substrates were used for this study, and SAM images of the results have been presented in previous articles [5][6][7]. Al2O3 layers were pre-annealed at 600 °C in N2 ambient conditions and then cleaned in megasonic de-ionized water before bonding.…”

Section: Bonding Condition Optimizationmentioning

confidence: 99%

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InGaAs-OI Substrate Fabrication on a 300 mm Wafer

Sollier

Widiez

Gaudin

et al. 2016

JLPEA

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In this work, we demonstrate for the first time a 300-mm indium-gallium-arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart Cut TM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 • C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer.

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Section: Fracture In the Inp Buffer Layersupporting

confidence: 60%

Section: Resultsmentioning

confidence: 99%

Section: Bonding Condition Optimizationmentioning

confidence: 99%

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InGaAs-OI Substrate Fabrication on a 300 mm Wafer

Sollier

Widiez

Gaudin

et al. 2016

JLPEA

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“…The donor wafer was subsequently removed by wet-etching, leaving a 200 mm InGaAs-on-insulator substrate. Very recently, a similar process but improved to allow donor wafer recycling was developed, leading to successful fabrication of 300 mm InGaAs-on-insulator substrates [62]. These processes open the way to very large-scale production of III-V-on-insulator hybrid substrates for future technology nodes.…”

Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Simentioning

confidence: 99%

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Lau

2017

Progress in Crystal Growth and Characterization of Materials

125

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Please note: Changes made as a result of publishing processes such as copy-editing, formatting and page numbers may not be reflected in this version. For the definitive version of this publication, please refer to the published source. You are advised to consult the publisher's version if you wish to cite this paper.This version is being made available in accordance with publisher policies. See http://orca.cf.ac.uk/policies.html for usage policies. Copyright and moral rights for publications made available in ORCA are retained by the copyright holders. U N C O R R E C T E D P R O O F ARTICLE INFO ABSTRACTMonolithic integration of III-V on silicon has been a scientifically appealing concept for decades. Notable progress has recently been made in this research area, fueled by significant interests of the electronics industry in high-mobility channel transistors and the booming development of silicon photonics technology. In this review article, we outline the fundamental roadblocks for the epitaxial growth of highly mismatched III-V materials, including arsenides, phosphides, and antimonides, on (001) oriented silicon substrates. Advances in hetero-epitaxy and selective-area hetero-epitaxy from micro to nano length scales are discussed. Opportunities in emerging electronics and integrated photonics are also presented.

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“…In order to improve the homogeneity and crystal quality of the top layer, a technology called as “Smart‐Cut” was later invented, where hydrogen ions, instead of oxygen ions, were implanted to single crystal semiconductor wafer. The implantation of hydrogen ions and subsequent annealing partially break the covalent bond at certain position (depends on the implantation energy) to form a mechanically cleavable plane, and thus, various semiconductor nanomembranes were fabricated with large area, high quality, and low cost …”

Section: Perspective Of Nanomembrane Technologymentioning

confidence: 99%

Assembly and Self‐Assembly of Nanomembrane Materials—From 2D to 3D

Huang

Mei

2018

Small

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Nanoscience and nanotechnology offer great opportunities and challenges in both fundamental research and practical applications, which require precise control of building blocks with micro/nanoscale resolution in both individual and mass-production ways. The recent and intensive nanotechnology development gives birth to a new focus on nanomembrane materials, which are defined as structures with thickness limited to about one to several hundred nanometers and with much larger (typically at least two orders of magnitude larger, or even macroscopic scale) lateral dimensions. Nanomembranes can be readily processed in an accurate manner and integrated into functional devices and systems. In this Review, a nanotechnology perspective of nanomembranes is provided, with examples of science and applications in semiconductor, metal, insulator, polymer, and composite materials. Assisted assembly of nanomembranes leads to wrinkled/buckled geometries for flexible electronics and stacked structures for applications in photonics and thermoelectrics. Inspired by kirigami/origami, self-assembled 3D structures are constructed via strain engineering. Many advanced materials have begun to be explored in the format of nanomembranes and extend to biomimetic and 2D materials for various applications. Nanomembranes, as a new type of nanomaterials, allow nanotechnology in a controllable and precise way for practical applications and promise great potential for future nanorelated products.

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300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology

Cited by 19 publications

References 30 publications

InGaAs-OI Substrate Fabrication on a 300 mm Wafer

InGaAs-OI Substrate Fabrication on a 300 mm Wafer

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Assembly and Self‐Assembly of Nanomembrane Materials—From 2D to 3D

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