300 ps 4K read-only memory implemented with AlGaAs/GaAs HBT technology

Kwok, C.Y.; Sheng, N.H.; Asbeck, P.M.

doi:10.1049/el:19940532

Cited by 3 publications

(5 citation statements)

References 2 publications

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“…假设有 n 个存储单元与高位线相连, 则与低位线 [12] 或者二极管逻辑的与门 (AND gate) [8] . 列行 0 1 2 3 4 5 6 7 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 2 0 0 1 1 0 0 0 1 3 0 0 1 与本文观察到现象类似 , 当同一列的数据为 "1111111011111110", 未被选中存储单元的漏电流减少位线上电流幅度 , 寄生电容的充放电时间增加 [11] .…”

Section: 电路设计与分析unclassified

“…列行 0 1 2 3 4 5 6 7 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 2 0 0 1 1 0 0 0 1 3 0 0 1 与本文观察到现象类似 , 当同一列的数据为 "1111111011111110", 未被选中存储单元的漏电流减少位线上电流幅度 , 寄生电容的充放电时间增加 [11] . 当输出序列为一长串"0"与少数"1", 或者相反 [1] InP HBT [11] CMOS [9] GaAs HBT [8] GaAs HBT [10] GaAs HBT (本文)…”

Section: 电路设计与分析unclassified

“…只读存储器 (read-only memory) [1] 、基于算术运算 (computational mapping) [2,3] 与基于算术运算的相位幅度转换电路 [3] 相比, 采用只读存储器与算术运算相结合的方法 [7] 可获得更高的无杂散动态范围. 但只读存储器工作速度达到合成频率的 2.5 倍 [8] , 成为直接数字频率合成器的速度瓶颈. 为提高大容量只读存储器的工作速度, 针对所采用制作工艺技术采取不同方法.…”

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应用于直接数字频率合成器的6-GHz GaAs HBT只读存储器

陈建武¹,

王丽²,

吴旦昱³

et al. 2011

Chin. Sci. Bull.

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Section: 电路设计与分析unclassified

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应用于直接数字频率合成器的6-GHz GaAs HBT只读存储器

陈建武¹,

王丽²,

吴旦昱³

et al. 2011

Chin. Sci. Bull.

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“…Bipolar decoders are typically built either from ECL NOR gates [12] with complemented inputs or from AND gates [8] using diode logic. For the diode AND gate, a static current is supplied through the input diodes, thus the output of the diode decoder begins to change as its inputs change, rather than once the inputs cross a threshold voltage.…”

Section: Row and Column Decodersmentioning

confidence: 99%

“…However, the ROM is often the limiting factor for the high speed of a DDFS, because it has to support clock rates in the order of two-and-half times the synthesized frequency [8]. Many technologies have been adopted to realize a high speed ROM with large size.…”

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A 6-GHz ROM suitable for DDFS application in GaAs HBT technology

Chen

Wang²,

et al. 2011

Chin. Sci. Bull.

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Read-only memory (ROM) is widely implemented as a phase-to-amplitude mapping block in direct digital frequency synthesizers (DDFS). This paper derives an equivalent model for the ROM in a DDFS to analyze and reduce the access time that is critical to the performance of the DDFS. Moreover, the signal skew observed in the simulation waveform is illustrated. The proposed 64×3-bit ROM is integrated as a part of an 8-bit DDFS, which operates functionally at 6 GHz. Measurement results demonstrate the improvement in the spur free dynamic range. Direct digital frequency synthesizers (DDFS) are widely used in communication systems, chirp radar systems, and phase array antennas. To exploit DDFSs in broadband communication systems, DDFS designs operating at GHz-range clock frequencies are required. A direct digital synthesizer can be implemented from a phase accumulator, a phaseto-amplitude mapping block, and a digital-to-analog converter. The phase-to-amplitude mapping block is the key to a high performance DDFS. Many architectures and designs for the phase-to-amplitude mapping block in a DDFS have been reported in the literature. Phase-to-amplitude mapping methods are mainly based on ROM-based designs [1], computational mapping designs [2,3], or both [4-6]. The increasing demand for higher speed DDFS circuits and the frequency limitations in CMOS technologies have necessitated the development of DDFSs implemented using heterojunction bipolar transistor (HBT) technology. Although indium phosphide (InP) HBT based circuits tend to work at a high frequency, high cost and low yield have limited the development of InP HBT based large scale integrated (LSI) circuits. Gallium arsenide (GaAs) HBT combining high frequency and high yield with a moderate price, shows prominent application in mixed-signal integrated circuits with a high level of complexity, such as the ultrahigh speed DDFS with high spur free dynamic range (SFDR).Comparing to a DDFS with computational mapping [3], the one with both ROM and computational mapping [7] was found to have a higher SFDR. However, the ROM is often the limiting factor for the high speed of a DDFS, because it has to support clock rates in the order of two-and-half times the synthesized frequency [8]. Many technologies have been adopted to realize a high speed ROM with large size. The fastest CMOS ROM reported, operates at a frequency up to 1.1 GHz [9]. A 64-bit, 5-GHz read-write look-up table (LUT) has been implemented in GaAs HBT [10], while an InP HBT 36-GHz, 16×6-bit ROM test circuit has also been

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