300mm wafer level sulfur monolayer doping for III&amp;#x2013;V materials

Loh, Wei‐Yip; Lee, R. T.P.; Tieckelmann, Robert; Orzali, Tommaso; Sapp, Brian; Hobbs, Chris; Rao, Satyavolu S. Papa; Fuse, Kazuhiko; Sato, Masanobu; Fujiwara, Nariaki; Chang, Lianxia; Uchida, H.

doi:10.1109/asmc.2015.7164438

Cited by 3 publications

(3 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The conformal nature of self-assembled monolayers provides the possibility to obtain a uniform doping profile for three dimension structures. Loh et al [65] reported that sulfur-contained inorganic salts (for example, sulfate and sulfite) were applied to dope the InAsGa thin layer.…”

Section: Monolayer Doping On Iii-v Semiconductorsmentioning

confidence: 99%

Dendrimers as Dopant Atom Carriers

Wu¹,

Dan²

2018

Dendrimers - Fundamentals and Applications

View full text Add to dashboard Cite

Properties of modern semiconducting transistors and future electron or quantum devices are essentially determined by single dopant atoms. How to precisely control the individual dopant position is one of the key factors to advance these technologies. In this chapter, we first briefly introduce the research progress in single dopant devices. To fabricate single dopant devices at large scale, we then overview our previous propose to control the locations of single dopants by self-assembly of large molecules (polyglycerols) with each carrying one dopant atom. The synthesis process, doping properties, and challenges of the molecular doping technique will be thoroughly elaborated before we conclude this chapter.

show abstract

Section: Monolayer Doping On Iii-v Semiconductorsmentioning

confidence: 99%

Dendrimers as Dopant Atom Carriers

Wu¹,

Dan²

2018

Dendrimers - Fundamentals and Applications

View full text Add to dashboard Cite

show abstract

“…To overcome the limitation of ion implantation for III-V fin doping, we developed a damage free sulfur-monolayer doping (S-MLD) process for III-V doping (40 -42). New sulfate-based S-MLD chemistries with lower Hazardous Materials Identification System (HMIS) profiles were also developed (43). This addresses the environmental, safety and health concerns of using sulfide-based S-MLD chemistries (40 -42) for high volume manufacturing (HVM).…”

Section: (B) Effect Of Active Doping Concentration On R Cmentioning

confidence: 99%

(Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs

Lee¹,

Loh²,

Tieckelmann³

et al. 2015

ECS Trans.

View full text Add to dashboard Cite

III-V semiconductors have emerged as the leading candidate to replace Si as the n-FET channel material for future low power logic applications. However, to realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (R ext ) be minimized. Among the different components of R ext , contact resistance (R C ), between metal and source/drain (S/D) junctions, has become the critical focus. Historically, multi-layered Au-based contacts (e.g. Au/Ge/III-V) are used in III-V processing to lower R C .However, the renewed interest in III-V semiconductors has attracted an increasing interest in developing Au-free contacts to III-V with low R C . In addition, a "silicide-like" metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it enables self-alignment and offers the option of using a common

show abstract

“…Additionally, ion implantation can lead to full amorphization of the fin and problematic recrystallization, resulting in defect formation and poor activation of the dopants 85 . Several alternative doping techniques have been investigated to overcome this issue: hot implantation 101 , plasma doping 103 , vapor phase deposition 104 , and solution-based monolayer doping 105,106 are examples. These alternative doping techniques will become even more relevant for subsequent technologies such as nanowires and vertical FETs.…”

Section: Challenges In Source Drain Contact Formationmentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

View full text Add to dashboard Cite

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

show abstract

300mm wafer level sulfur monolayer doping for III–V materials

Cited by 3 publications

References 7 publications

Dendrimers as Dopant Atom Carriers

Dendrimers as Dopant Atom Carriers

(Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs

Scaling Challenges for Advanced CMOS Devices

Contact Info

Product

Resources

About