300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications

Jourdain, Anne; Buisson, Thibault; Phommahaxay, Alain; Privett, Mark; Wallace, Dan; Sood, Sumant; Bisson, Peter; Beyne, Eric; Travaly, Youssef; Swinnen, Bart

doi:10.1109/3dic.2010.5751468

Cited by 15 publications

(6 citation statements)

References 2 publications

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“…5 with surface plot and in the Fig. 6 with a radius plot are comparable to or better than the ones obtained previously with the HT-10.10 thermoplastic material from Brewer Science [2]. Indeed raw TTV values of less than 2μm have been obtained with a 16-fold increased surface resolution compared to [2].…”

Section: B Wafer Thinningsupporting

confidence: 75%

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Phommahaxay

Jourdain

Verbinnen

et al. 2012

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International

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Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on a novel ZoneBOND approach to face these challenges.

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Section: B Wafer Thinningsupporting

confidence: 75%

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Phommahaxay

Jourdain

Verbinnen

et al. 2012

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International

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“…Key concerns with such thin silicon layers are cracking and stress-related problems. The handling of these thin and fragile wafers requires the development of reliable wafer carrier systems and low-stress passivation layers [23].…”

Section: Thinning-related Reliability Concernsmentioning

confidence: 99%

Reliability Challenges Related to TSV Integration and 3-D Stacking

Croes

Messemaeker

et al. 2016

IEEE Des. Test

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Imec's view on the key reliability issues related to 3D integration is discussed. First, throughsilicon via (TSV) reliability concerns linked to thermo-mechanical stresses induced in copper and silicon and to TSV barrier/liner integrity are considered. Then, the possible impact of the TSV on the performance and reliability of nearby devices and interconnects is addressed. After that, reliability concerns related to wafer thinning and backside processing are covered by discussing the effect of stress release in exposed copper nails and the impact of backside passivation and copper contamination on devices. Finally, reliability issues caused by 3D stacking are discussed. KeywordsThrough Silicon Via; Wafer Thinning; 3D-Stacking; Reliability; IntroductionWhile IC dimension scaling leads to faster transistors, the performance of the whole integrated circuit is becoming more and more affected by the increasing signal delay associated with the cross-section scaling of on-chip and off-chip interconnects. 3D integration is one of the most promising technology candidates to mitigate the so-called interconnect bottleneck. With 3D integration, chips are stacked on top of each other, leading to a significant sleek form factor reductions [1][2]. Electrical connections between different stacked chips are made by vertical conductors, the so-called TSVs [3][4], with typical diameters and depths in the range between 2-20m and 10-100m, respectively, in leading-edge processes. TSVs can be processed at different phases of the chip fabrication. With via-first integration, the TSV is fabricated before

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“…Firstly, 0.7mm thickness glass is treated with a release layer beforehand [5], the bonding material is coated on the carrier as the next step. The release layer, an organic polymer, is the only material required to treat the surface of glass carrier to enable laser debonding at room temperature.…”

Section: Thin Glass Bonding Modificationmentioning

confidence: 99%

Laminating thin glass onto glass carrier to eliminate grinding and bonding process for glass interposer

Tsai¹,

Wang²,

Shorey³

et al. 2014

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)

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Interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and the substrate [1]. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE as well as the ability to provide a low cost solution [2].In this investigation, another cost reduction concept of through glass via (TGV) wafer processing is being studied. By leveraging current semiconductor equipment and knowhow, we bond TGV wafers onto glass carriers as shown in Figure 1, the TGV wafer thickness is directly 100um and center diameter (CD) of through glass via is 30 m. This approach provides a method to temporarily bond these TGV wafers to glass carriers enabling handling through processes such as via fill and surface metallization. The ability to form glass at the target 100 um thickness and provide through holes and thus avoid backgrinding processes provides substantial opportunity to save costs and avoid yield loss.

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300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications

Cited by 15 publications

References 2 publications

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Reliability Challenges Related to TSV Integration and 3-D Stacking

Laminating thin glass onto glass carrier to eliminate grinding and bonding process for glass interposer

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300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications

Cited by 15 publications

References 2 publications

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND&#x2122; temporary bonding process with room temperature peel debonding

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND&#x2122; temporary bonding process with room temperature peel debonding

Reliability Challenges Related to TSV Integration and 3-D Stacking

Laminating thin glass onto glass carrier to eliminate grinding and bonding process for glass interposer

Contact Info

Product

Resources

About

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding