2018
DOI: 10.1109/lssc.2019.2910468
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34.3 fJ/conv.-step 8-MHz Bandwidth Fourth-Order Pseudo-Differential Ring-Amplifier-Based Continuous-Time Delta–Sigma ADC in 65 nm

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Cited by 5 publications
(3 citation statements)
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“…Figure 7(c) illustrates FoM variation over V in n ½ sweep from 8:2 fJ=conv to 0:89 fJ=conv. This result is in the same order of the magnitude of state-of-the-art analog-to-digital RD converters [34]. Towards a neuromorphic computing, one could use the NAPS proposal combined to a time-todigital converter and digital-based spiking neural networks like [4] in the perspective of a mixed-signal solution as [2], but still ensure a FoM in fJ=conv range.…”
Section: Nasp Simulationsmentioning
confidence: 79%
“…Figure 7(c) illustrates FoM variation over V in n ½ sweep from 8:2 fJ=conv to 0:89 fJ=conv. This result is in the same order of the magnitude of state-of-the-art analog-to-digital RD converters [34]. Towards a neuromorphic computing, one could use the NAPS proposal combined to a time-todigital converter and digital-based spiking neural networks like [4] in the perspective of a mixed-signal solution as [2], but still ensure a FoM in fJ=conv range.…”
Section: Nasp Simulationsmentioning
confidence: 79%
“…Care must be taken to assure that the transistors are operating in the saturation region and not in the triode region. This is because the triode region causes the transistor to behave in a non-linear fashion leading to poor transient response as well as the reduction of the overall gain [27]. The layout of the two-stage amplifier is shown in Figure 2.…”
Section: Circuit Design Of Conventional Delta-sigma Adc 21 Two Stagmentioning
confidence: 99%
“…Several existing techniques in ΔΣ ADC architecture reduce the power consumption at the cost of speed [25][26][27][28][29]. Hence the performance of ADC can be improved by transferring the signal processing task to digital domain and by applying proper scaling methodology.…”
mentioning
confidence: 99%