350°C CMOS logic process

Abstract

A d i e l e c t r i c a l l y i s o l a t e d s e l f -a l i g n e d s i l i c o n g a t e CMOS process designed f o r h i g h temperature operation i s d e 8 c r i bed. Component c h a r a c t e r i s t i c s o v e r t h e 25 C t o 325OC range a r e p r e s e n t e d . C i r c u i t o p e r a t i o n t o 38OoC i s demonstrated. C i r c u i t and process modifications which could extend operating temperature to about 45OoC are suggested.

TexSe1–x Photodiode Shortwave Infrared Detection and Imaging

“…Considering the integration with CMOS, we limited the annealing temperature below 350 °C. [ 66 ] As the annealing temperature increases from 200 to 240 °C, the grain shape changes from irregular grains to strip‐shaped grains (Figure 2a–d), deriving from the 1D crystal structure (Figure 1a). The similar phenomenon has also been observed in other 1D crystal‐structural materials, such as Sb 2 Se 3 and Sb 2 S 3 .…”