3C-SiC Transistor With Ohmic Contacts Defined at Room Temperature

Li, Fan; Sharma, Yogesh; Walker, David; Hindmarsh, Steven A.; Jennings, Michael R.; Martin, David; Fisher, C; Gammon, P. M.; Pérez‐Tomás, Amador; Mawby, P.A.

doi:10.1109/led.2016.2593771

Cited by 13 publications

(10 citation statements)

References 36 publications

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“…Ohmic metallisation was obtained by RIE etching the passivation oxide and evaporating first a 30 nm Ti layer, followed by a 100 nm Ni layer on the N+ regions. A rapid thermal anneal at 1000 ºC for 2 mins in Ar was performed to form the ohmic contact with specific contact resistance below 1×10 -5 Ω.cm 2 [31]. Finally, the gate contact was defined by selectively evaporating 500 nm thick Al above the gate oxide region.…”

Section: Methodsmentioning

confidence: 99%

“…In the last ten years, there have been many improvements in 3C-SiC substrate preparation [18][19][20][21][22][23][24] that a defect density below 400 cm -1 became possible [24]. There were also further developments in 3C-SiC device processing, including implantation [25,26], oxidation [27][28][29], and metallisation [30,31]. 600 V vertical power MOSFET was demonstrated with a specific on-resistance of 8.2 mΩ.cm 2 [32].…”

Section: Introductionmentioning

confidence: 99%

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A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability

Mawby

Qiu

et al. 2020

IEEE Trans. Electron Devices

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Despite the recent advances in 3C-SiC technology, there is a lack of statistical analysis on the reliability of SiO2 layers on 3C-SiC, which is crucial in power MOS device developments. This paper presents a comprehensive study of the medium and long-term time-dependent dielectric breakdown (TDDB) of 65 nm thick SiO2 layers thermally grown on a state-of-the-art 3C-SiC/Si wafer. Fowler-Nordheim (F-N) tunnelling is observed above 7 MV/cm and an effective barrier height of 3.7 eV is obtained, which is highest known for native SiO2 layers grown on the semiconductor substrate. The observed dependence of the oxide reliability on the gate active area suggests the oxide quality has not reached the intrinsic level. Three failure mechanisms were identified, confirmed by both medium and long-term results. Whereas two of them are likely due to extrinsic defects from material quality and fabrication steps, the one dominating the high field (>8.5 MV/cm) should be attributed to the electron impact ionization within SiO2. At room temperature, the field acceleration factor is found to be ≈0.906 dec/ (MV/cm) for high fields, and the projected lifetime exceeds 10 years at 4.5 MV/cm.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability

Mawby

Qiu

et al. 2020

IEEE Trans. Electron Devices

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“…Noting that Ni 2 Si (121) is readily formed at 600 °C, with no other noticeable phases above that temperature, the Ni 2 Si (002) enhanced phase could explain the contact resistance reduction from 800 °C to 1000 °C. It is worth mentioning that, due to the very low SBH of highly doped n-type 3C-SiC/metal interface, as-deposited ohmic contacts can be obtained without PMA processing [ 59 , 65 ]. This makes it possible to integrate SiC transistor technologies with other low temperature technologies, such as atomic layer deposited high k dielectrics (e.g., HfO 2 or Al 2 O 3 ) with relatively low growth temperatures and classic wafer bonded or heterojunction devices.…”

Section: Processing Technology For 3c-sicmentioning

confidence: 99%

“…High field-effect mobility values were demonstrated by fabricating 3C-SiC MOSFETs with a high current density of 1220 A/cm 2 and encouraging scaling features were shown in 1 mm × 1 mm and 3 mm × 3 mm devices [ 74 ]. In addition, it is shown in [ 65 , 68 ] that by removing the rapid thermal anneal for the ohmic contact, the field-effect mobility can be further improved. Despite the achievements made in forward conditions, reaching blocking ability (BV) close to the theoretical values is still a challenge, mainly because of the high leakage current induced by crystal defects such as SFs [ 97 ].…”

Section: 3c-sic Device Prototypesmentioning

confidence: 99%

Status and Prospects of Cubic Silicon Carbide Power Electronics Device Technology

Li¹,

Roccaforte

Greco

et al. 2021

Materials

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Wide bandgap (WBG) semiconductors are becoming more widely accepted for use in power electronics due to their superior electrical energy efficiencies and improved power densities. Although WBG cubic silicon carbide (3C-SiC) displays a modest bandgap compared to its commercial counterparts (4H-silicon carbide and gallium nitride), this material has excellent attributes as the WBG semiconductor of choice for low-resistance, reliable diode and MOS devices. At present the material remains firmly in the research domain due to numerous technological impediments that hamper its widespread adoption. The most obvious obstacle is defect-free 3C-SiC; presently, 3C-SiC bulk and heteroepitaxial (on-silicon) display high defect densities such as stacking faults and antiphase boundaries. Moreover, heteroepitaxy 3C-SiC-on-silicon means low temperature processing budgets are imposed upon the system (max. temperature limited to ~1400 °C) limiting selective doping realisation. This paper will give a brief overview of some of the scientific aspects associated with 3C-SiC processing technology in addition to focussing on the latest state of the art results. A particular focus will be placed upon key process steps such as Schottky and ohmic contacts, ion implantation and MOS processing including reliability. Finally, the paper will discuss some device prototypes (diodes and MOSFET) and draw conclusions around the prospects for 3C-SiC devices based upon the processing technology presented.

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“…In the past, Ohmic contacts formed using annealed Nickel-and Titanium-based metallic layers have been investigated on n-type heavily doped 3C-SiC layers, grown on different substrates [9, 12 , 13 ]. Very recently, Ohmic contacts were obtained on heavily doped (degenerate) n-type implanted 3C-SiC without annealing and applied to 3C-SiC MOSFETs fabrication [14]. However, only a limited work has been reported on moderately doped ntype 3C-SiC and on p-type doped 3C-SiC [15,16].…”

Section: Introductionmentioning

confidence: 99%

Ohmic contacts on n-type and p-type cubic silicon carbide (3C-SiC) grown on silicon

Spera

Greco

Nigro

et al. 2019

Materials Science in Semiconductor Processing

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This paper is a report on Ohmic contacts on n-type and p-type type cubic silicon carbide (3C-SiC) layers grown on silicon substrates. In particular, the morphological, electrical and structural properties of annealed Ni and Ti/Al/Ni contacts has been studied employing several characterization techniques. Ni films annealed at 950°C form Ohmic contacts on moderately n-type doped 3C-SiC (ND ~ 1×10 17 cm -3 ), with a specific contact resistance of 3.7×10 -3 Ωcm 2 . The main phase formed upon annealing in this contact was nickel silicide (Ni2Si), with randomly dispersed carbon in the reacted layer. In the case of a p-type 3C-SiC with a high doping level (NA ~ 5×10 19 cm -3 ), Ti/Al/Ni contacts were preferable to Ni ones, as they gave much lower values of the specific contact resistance (1.8 ×10 -5 Ωcm 2 ). Here, an Al3Ni2 layer was formed in the uppermost part of the contact, while TiC was detected at the interface. For this system, a temperature dependent electrical characterization allowed to establish that the thermionic field emission rules the current transport at the interface. All these results can be useful for the further development of a devices technology based on the 3C-SiC polytype.

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3C-SiC Transistor With Ohmic Contacts Defined at Room Temperature

Cited by 13 publications

References 36 publications

A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability

A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability

Status and Prospects of Cubic Silicon Carbide Power Electronics Device Technology

Ohmic contacts on n-type and p-type cubic silicon carbide (3C-SiC) grown on silicon

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