Proceedings of the 16th International Workshop on Vertex Detectors — PoS(Vertex 2007) 2008
DOI: 10.22323/1.057.0017
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3d circuit integration

Abstract: High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are… Show more

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Cited by 12 publications
(3 citation statements)
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“…The approach is still emerging and needs to be assessed, especially for its material budget and power dissipation. Within a consortium led by FERMILAB, different architectures were submitted for fabrication, which try to combine high level signal processing with low power dissipation [8].…”
Section: Cmos Pixel Sensors For High Precision Beam Telescopes and Vementioning
confidence: 99%
“…The approach is still emerging and needs to be assessed, especially for its material budget and power dissipation. Within a consortium led by FERMILAB, different architectures were submitted for fabrication, which try to combine high level signal processing with low power dissipation [8].…”
Section: Cmos Pixel Sensors For High Precision Beam Telescopes and Vementioning
confidence: 99%
“…In the "ILC-class" SDR0 chip, the sparsified readout architecture is based on a token passing scheme, which was first implemented by Fermilab IC designers in the VIP chip [9]. This architecture is tailored on the ILC beam structure and is presently based on the assumption that there is a very low probability that a pixel is hit more than once during a bunch train period.…”
Section: Digital Readout Architecturementioning
confidence: 99%
“…The second approach is based on a technology leap exploiting vertical integration processes [9], which promise to overcome typical limitations of standard MAPS as well as of DNW MAPS. In the framework of a consortium between Fermilab, IN2P3 and INFN, the first step in this direction is planned to be the fabrication of a two-tier DNW MAPS by the face-to-face bonding of two 130 nm CMOS wafers.…”
Section: Jinst 4 P03005 4 Future Dnw Maps Developmentsmentioning
confidence: 99%