3D nanowire gate-all-around transistors: Specific integration and electrical features

Growth kinetics of SiGe/Si superlattices on bulk and silicon-on-insulator substrates for multi-channel devices

“…Of note are the double-gate [1], the localized silicon-on-insulator (L-SOI) [2], the silicon-on-nothing (SON) [3], the multi-channel (MC) [4,5] and the three-dimensional nano-wires (3D-NW) [6][7][8] devices. They all rely on (i) the (selective) epitaxy of SiGe/Si multilayers [9][10][11], (ii) the anisotropic etching of the active area [12] and (iii) the high degree of selectivity (versus Si) that can be achieved when laterally etching the SiGe layers (with Ge contents above 15%) [13][14][15][16][17].…”

Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model

“…Recently, a multichannel structure with GAA configuration has been proposed as a candidate for the highperformance devices with a high current drivability ≈2.2 mA/µm reported [50]. Recent works explored the vertical stacking of Si nanowires [51] with multiple channels; another work obtained an enhanced electrostatic control by using a gate-all-around configuration [52].…”

Electron tomography of gate-all-around nanowire transistors

“…However, as gate lengths are reduced below 50nm, short channel effects become increasingly significant, and high leakage currents become a problem. One promising solution to this is the gate-all-around (GAA) architecture [1]. The fabrication of these devices involves gate stack integration around semiconductor nanowires, as seen in figures 1 and 2.…”