3D Sequential Integration: Application-driven technological achievements and guidelines

Batude, P.; Brunet, Laurent; Fenouillet-Béranger, C.; Andrieu, F.; Colinge, J.P.; Lattard, Didier; Vianello, E.; Thuries, Sébastien; Billoint, Olivier; Vivet, Pascal; Santos, Carla Eliete Iochims dos; Bauchy, Mathieu; Sklénard, B.; Lu, Chang Ming; Micout, J.; Deprat, F.; Mercado, E; Ponthenier, F.; Rambal, N.; Samson, M-P.; Cassé, Maxime; Hentz, Sébastien; Arcamone, Julien; Sicard, Gilles; Hutin, L.; Pasini, L.; Ayres, A.; Rozeau, O.; Berthelon, R.; Nemouchi, F.; Rodriguez, Philippe; Pin, J. B.; Larmagnac, D.; Duboust, Alain; Ripoche, V.; Barraud, S.; Allouti, N.; Barnola, S.; Vizioz, C.; Hartmann, J.-M.; Kerdilès, S.; Acosta-Alba, P.; Beaurepaire, S.; Beugin, V.; Fournel, Frank; Besson, P.; Loup, V.; Gassilloud, R.; Martín, F.; Garros, X.; Mazen, F.; Prévitali, B.; Euvrard-Colnat, C.; Balan, V.; Comboroure, C.; Zussy, M.; Mazzocchi,; Faynot, O.; Vinet, Maud

doi:10.1109/iedm.2017.8268316

Cited by 53 publications

(17 citation statements)

References 2 publications

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“…4 TMD materials are also promising with respect to the integration of memory, logic, photonic, sensor, and general input/output functions above conventional silicon-integrated circuits in the back-end-of-line (BEOL) provided low thermal budget processes can be developed at ≤400°C. 5 2D atomic crystals of platinum diselenide (PtSe 2 ) exhibit distinct electronic structures and properties. PtSe 2 is a layered material in which individual atomic layers are stacked together by van der Waals (vdW) interactions.…”

Section: Introductionmentioning

confidence: 99%

Quantum confinement-induced semimetal-to-semiconductor evolution in large-area ultra-thin PtSe2 films grown at 400 °C

et al. 2019

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In this work, we present a comprehensive theoretical and experimental study of quantum confinement in layered platinum diselenide (PtSe 2 ) films as a function of film thickness. Our electrical measurements, in combination with density functional theory calculations, show distinct layer-dependent semimetal-to-semiconductor evolution in PtSe 2 films, and highlight the importance of including van der Waals interactions, Green's function calibration, and screened Coulomb interactions in the determination of the thickness-dependent PtSe 2 energy gap. Large-area PtSe 2 films of varying thickness (2.5-6.5 nm) were formed at 400°C by thermally assisted conversion of ultra-thin platinum films on Si/SiO 2 substrates. The PtSe 2 films exhibit p-type semiconducting behavior with hole mobility values up to 13 cm 2 /V·s. Metal-oxide-semiconductor field-effect transistors have been fabricated using the grown PtSe 2 films and a gate field-controlled switching performance with an I ON /I OFF ratio of >230 has been measured at room temperature for a 2.5-3 nm PtSe 2 film, while the ratio drops to <2 for 5-6.5 nm-thick PtSe 2 films, consistent with a semiconductingto-semimetallic transition with increasing PtSe 2 film thickness. These experimental observations indicate that the low-temperature growth of semimetallic or semiconducting PtSe 2 could be integrated into the back-end-of-line of a silicon complementary metaloxide-semiconductor process.npj 2D Materials and Applications (2019) 3:33 ; https://doi.

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Section: Introductionmentioning

confidence: 99%

Quantum confinement-induced semimetal-to-semiconductor evolution in large-area ultra-thin PtSe2 films grown at 400 °C

et al. 2019

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“…Compared to 3D packaging using throughsilicon vias, where levels are fabricated in parallel, then bonded together with low-resolution alignment, 3DS integration allows for alignment of subsequent levels as well as highly dense inter-level interconnects limited only by the resolution of the stepper. 3DS integration facilitates not only traditional scaling motivators [2]- [4], such as power density and delay reduction through shorter interconnects, but also "More than Moore" approaches, such as monolithic integration of functionally different layers, e.g., for photonics, RF and sensing. Key challenges of this technology include thermal budget management [5] and integration of channel layers with low defect density.…”

Section: Introductionmentioning

confidence: 99%

InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

Convertino

Zota

Caimi

et al. 2019

IEEE J. Electron Devices Soc.

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In this paper, we demonstrate InGaAs FinFETs 3-D sequentially (3DS) integrated on top of a fully depleted silicon-on-insulator CMOS. Top layer III-V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. We demonstrate that the low thermal budget of the top layer process does not affect the lower level FETs performance. An on-current of 200 μA/μm (at I OFF = 100 nA/μm and V DD = 0.5 V) is achieved, representing the highest reported for 3DS integrated III-V FETs on silicon, showing a 50% improvement in R ON compared to previous work. The achieved improved performance can be attributed to the introduction of spacers, doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.

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“…Although, until today, 3D stacking is predominantly used for 3D CIS, constraints concerning the alignment capabilities cannot allow more aggressive pixel miniaturization, which is required for future CIS generations [3,4]. However, in the case of 3D Sequential Integration (3DSI) [5,6], where one tier is processed on top of the other instead of being stacked, this drawback can be overcome, achieving pixel partitioning with state-of-the-art pixel pitch. In addition, 3DSI offers 3D contacts of outstanding high-density between tiers (up to 10 8 3D via/mm 2 ), enabling partitioning with high connectivity and low latency.…”

Section: Introductionmentioning

confidence: 99%

Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel

et al. 2022

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In this paper, we present a thorough analysis of parasitic coupling effects between different electrodes for a 3D Sequential Integration circuit example comprising stacked devices. More specifically, this study is performed for a Back-Side Illuminated, 4T–APS, 3D Sequential Integration pixel with both its photodiode and Transfer Gate at the bottom tier and the other parts of the circuit on the top tier. The effects of voltage bias and 3D inter-tier contacts are studied by using TCAD simulations. Coupling-induced electrical parameter variations are compared against variations due to temperature change, revealing that these two effects can cause similar levels of readout error for the top-tier readout circuit. On the bright side, we also demonstrate that in the case of a rolling shutter pixel readout, the coupling effect becomes nearly negligible. Therefore, we estimate that the presence of an inter-tier ground plane, normally used for electrical isolation, is not strictly mandatory for Monolithic 3D pixels.

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3D Sequential Integration: Application-driven technological achievements and guidelines

Cited by 53 publications

References 2 publications

Quantum confinement-induced semimetal-to-semiconductor evolution in large-area ultra-thin PtSe2 films grown at 400 °C

Quantum confinement-induced semimetal-to-semiconductor evolution in large-area ultra-thin PtSe2 films grown at 400 °C

InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel

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