3D-stacked Strained SiGe/Ge Gate-All-Around (GAA) Structure Fabricated by 3D Ge Condensation

Reduction of process temperature for Si surface flattening utilizing Ar/H2ambient annealing and its application to SOI-MISFETs with bilayer HfN high-k gate insulator

“…The advanced metal-oxide-semiconductor field-effect transistors (MOSFETs) have been scaled down to 20 nm or beyond with the ultra-thin body (UTB) Si-on-insulator (SOI) structure or 3D gate structure. [1][2][3][4][5][6][7][8][9][10] It is necessary for the ultra-thin gate insulator to be introduced for the scaled devices, even for the 3D gate FinFET. In the International Roadmap for Devices and Systems (IRDS), the inversion layer thickness of 0.9 nm is required in 2028, which corresponds to the equivalent oxide thickness (EOT) of 0.5 nm or below.…”