2015
DOI: 10.1108/mi-11-2014-0050
|View full text |Cite
|
Sign up to set email alerts
|

3D system-in-package design using stacked silicon submount technology

Abstract: Purpose -This study aims to provide a flexible and cost-effective solution of 3D heterogeneous integration for applications such as micro-electro-mechanical system (MEMS) applications and smart sensor systems. Design/methodology/approach -A novel 3D system-in-package (SiP) based on stacked silicon submount technology was successfully developed and well-demonstrated by the fabrication and assembly process of a selected smart lighting module. Findings -The stacked module consists of multiple layers of silicon su… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
4
0

Year Published

2016
2016
2021
2021

Publication Types

Select...
5
2

Relationship

1
6

Authors

Journals

citations
Cited by 8 publications
(4 citation statements)
references
References 21 publications
0
4
0
Order By: Relevance
“…There are many interconnection technologies such as wire bonding, edge connects, and capacitive or inductive coupling methods that could be used to fabricate 3D-IC devices [2,3]. However, the most promising technology for fabricating 3D-IC packages is the through-silicon-via (TSV) technology, where the TSVs are used for power delivery and signal exchange between the stacked chips [4,5]. TSV technologies have already been shown successful in reducing signal delay, enhancing IC integration and decreasing the overall packaging volume [6].…”
Section: Introductionmentioning
confidence: 99%
“…There are many interconnection technologies such as wire bonding, edge connects, and capacitive or inductive coupling methods that could be used to fabricate 3D-IC devices [2,3]. However, the most promising technology for fabricating 3D-IC packages is the through-silicon-via (TSV) technology, where the TSVs are used for power delivery and signal exchange between the stacked chips [4,5]. TSV technologies have already been shown successful in reducing signal delay, enhancing IC integration and decreasing the overall packaging volume [6].…”
Section: Introductionmentioning
confidence: 99%
“…The presented silicon submount approach should provide satisfying reliability by easing the thermal management. More detailed results were discussed in the previous work (Dong et al , 2013, 2015).…”
Section: Applications and Discussionmentioning
confidence: 78%
“…By using the 3S technology, highly compact modules with system function are aimed to be achieved at reasonable cost. A smart lighting system (Dong et al , 2013, 2015) and particulate matter (PM) sensor system (Dong et al , 2017, 2016) were chosen as development demo in this paper.…”
Section: Introductionmentioning
confidence: 99%
“…There are many interconnection technologies such as wire bonding, edge connect and capacitive or inductive coupling method to fabricate 3D-IC devices [23,24]. However, the most key technology for enabling 3D-IC package is throughsilicon via (TSV) technology which acts as paths for signal exchange and power delivery between the stacked chips [25,26]. TSV technology has allowed great progress in reducing signal delay, enhancing the IC integration and decreasing the overall packaging volume [27].…”
Section: Cnt-based Interconnectsmentioning
confidence: 99%