3D System Integration by Chip-to-Wafer Stacking Technologies

Ramm, Peter; Klumpp, Armin; Merkel, Reinhard; Weber, Josef; Wieland, Robert; Elst, Günter

doi:10.7567/ssdm.2003.g-4-1

Cited by 4 publications

(4 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Three-dimensional (3D) chip-stacking technology is attracting a great deal of attention for realizing advanced, high-speed, compact, and highly functional electronic systems. [1][2][3][4][5] To realize the three-dimensionally stacked-chip system, a bonding technology that can form a number of bump connections with a pitch below 20 mm is required.…”

Section: Introductionmentioning

confidence: 99%

Pyramid Bumps for Fine-Pitch Chip-Stack Interconnection

Watanabe

Ootani

Asano

2005

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

We propose pyramid bumps as one of the compliant bumps for realizing stacked chips with fine-pitch chip interconnections. The pyramid bumps, made of Au, are fabricated by the bump transfer method. The bump size is approximately 13 µm at the base and pitch is 20 µm. A comparative study between the pyramid bump and the conventional plated bump is carried out. It is demonstrated that the pyramid bump deforms more easily than the plated bump. This indicates that the pyramid bump has a significant advantage over the plated bump in compensating the bump height deviation and the nonuniformity in bonding pressure and that the bonding of a pyramid bump can be achieved at smaller pressing loads than those necessary for a plated bump. It is also found that the pyramid bump effectively excludes insulating resin, which is precoated on the chip surface, from the bonding interface and thereby suppresses bonding failure.

show abstract

Section: Introductionmentioning

confidence: 99%

Pyramid Bumps for Fine-Pitch Chip-Stack Interconnection

Watanabe

Ootani

Asano

2005

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…ESPN consists of one multiprocessor chip and two laser source chips connected by off-chip optical fibers and electrical wires on the PCB. The multiprocessor chip consists of three vertically stacked dies using 3D packaging technology [10]. The processor and caches die contains processor cores, private L1/L2 caches and electrical routers.…”

Section: An Overview Of Espnmentioning

confidence: 99%

ESPN: A case for energy-star photonic on-chip network

2013

International Symposium on Low Power Electronics and Design (ISLPED)

View full text Add to dashboard Cite

Photonic Network-on-Chips (NoCs) have recently been proposed due to their inherent low latency and high bandwidth. However, the high static power of the photonic components (e.g. laser source, resonators and waveguides) often results in energyinefficient architectures. In this paper, we advocate the EnergyStar Photonic Network (ESPN) architecture that optimizes energy utilization via a two-pronged approach: (1) by enabling dynamic resource provisioning, ESPN adapts photonic network resources based on runtime traffic characteristics and (2) by utilizing all-optical adaptive routing, ESPN improves energy efficiency by intelligently exploiting existing network resources without introducing high latency and power hungry auxiliary routing mechanisms. Our evaluation results show that compared to the baseline design, ESPN reduces power and energy consumption under synthetic traffic patterns by 50% and 58% respectively.

show abstract

“…Three dimensional (3D) chip-stacking technology is attracting a great deal of attention for realizing advanced high-speed, compact, and highly functional electronic systems. [1][2][3][4][5] For the development and the quality control of 3D stacked-chip systems, testing of bump connections is necessary. The connection test becomes important particularly when the process margin of the bonding process (such as the alignment margin, the parallelism between the chip holding tool and stage of the bonding machine, and the bump height deviation) becomes small.…”

Section: Introductionmentioning

confidence: 99%

Connection Test of Area Bump Using Active-Matrix Switches

Watanabe

Hasegawa

Asano

2005

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

We propose a new method of bump connection testing using active-matrix metal oxide semiconductor field-effect transistor (MOSFET) switches. One of the bump connections is electrically selected using the active-matrix switches and the current-voltage characteristic between chips is measured through the selected bump connection. In this method, the testing of the individual bumps and the investigation of the bonding failure mechanism are possible. This method can also be applied to the actual chip because the chip can be electrically separated from a test circuit using active-matrix MOSFET switches.

show abstract

3D System Integration by Chip-to-Wafer Stacking Technologies

Cited by 4 publications

References 0 publications

Pyramid Bumps for Fine-Pitch Chip-Stack Interconnection

Pyramid Bumps for Fine-Pitch Chip-Stack Interconnection

ESPN: A case for energy-star photonic on-chip network

Connection Test of Area Bump Using Active-Matrix Switches

Contact Info

Product

Resources

About