3D system integration on 300 mm wafer level: High-aspect-ratio TSVs with ruthenium seed layer by thermal ALD and subsequent copper electroplating

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

“…1, the pressing issue is the conformal deposition of BS layers in high aspect ratio (HAR) TSV with AR > 10, and it is becoming increasingly difficult even with ALD. 26) Especially the deposition temperature for Ni using ALD techniques varies from 180 °C27) to 300 °C28) depending on type of precursors, and to our knowledge the growth of Ni inside the deep trenches with aspect ratio >10 has not been reported till to-date. The via-last TSV process involves temporary bonding and debonding of the wafer of interest using organic glue materials, it is important to keep the liner and BS layer film deposition temperatures well below 200 °C.…”

Autocatalytic Deposition of Nickel–Boron Diffusion Barrier onto Diazonium-Treated SiO2 for High Aspect Ratio Through-Silicon Via Technology in 3D Integration

“…The pursuit of high-density integration has led to the adoption of high aspect ratio (HAR) TSVs, exceeding 10. For the feasibility of 3D integration with Cu-filled TSVs featuring high aspect ratios, the challenges of poor step-coverage and inadequate adhesion of the seed and/or barrier layers must be effectively addressed. − …”

“…Conventional methods such as sputtering, physical vapor deposition (PVD), and chemical vapor deposition (CVD) have limitations, especially beyond a certain aspect ratio, where achieving conformal coatings becomes challenging. − Atomic layer deposition (ALD) is known for providing conformal coatings but requires expensive equipment and operates at elevated wafer temperatures, limiting its applicability . As a result, advancements in microelectro-mechanical systems (MEMS) employing 3D integration and TSV technologies demand innovative and cost-effective methods capable of delivering high aspect ratio TSVs with highly conformal and strongly adhesive barrier/seed layers. ,, …”

Effects of amplitude modulated capacitively coupled discharge Ar plasma on kinetic energy and angular distribution function of ions impinging on electrodes: particle-in-cell/Monte Carlo collision model simulation

“…The common features for almost TSV integration processes are as follows: 4,5) silicon wafer etching by a deep reactive ion etching (RIE), the deposition of an insulator liner on sidewalls customarily by the chemical vapor deposition (CVD) method, and the formation of a conductive layer which generally consists of the deposition of diffusion barrier metal and copper seed layer, and via filling though copper electroplating. Nowadays, these TSV key films are depending on plasmaenhanced CVD (PECVD), [6][7][8][9][10] physical vapor deposition (PVD), 11) atomic layer deposition (ALD) [12][13][14][15] and plasmaenhanced ALD (PEALD) [16][17][18] system. Those deposition methods are not able to answer the actual TSV needs.…”