3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding

Oprins, Herman; Cherman, Vladimir; Webers, Tomas; Kim, Soon-Wook; Vos, Joeri De; Plas, G. Van der; Beyne, Eric

doi:10.1109/itherm45881.2020.9190392

Cited by 16 publications

(6 citation statements)

References 23 publications

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“…All vias are filled with bulk Cu with a diameter of 20 μm. The TIR between chip layers 1 and 2 is 0.5 mm 2 K/W, based on studies on relevant 3D bonding interfaces [ 16 ]. The Newtonian cooling process was enhanced by the TDV chip backside surface with an effective heat transfer coefficient of 15 kW/m 2 K at an ambient temperature of 20 °C.…”

Section: Resultsmentioning

confidence: 99%

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Bottom-Up Cu Filling of High-Aspect-Ratio through-Diamond vias for 3D Integration in Thermal Management

Zhao

Wei

et al. 2023

Micromachines

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Three-dimensional integrated packaging with through-silicon vias (TSV) can meet the requirements of high-speed computation, high-density storage, low power consumption, and compactness. However, higher power density increases heat dissipation problems, such as severe internal heat storage and prominent local hot spots. Among bulk materials, diamond has the highest thermal conductivity (≥2000 W/mK), thereby prompting its application in high-power semiconductor devices for heat dissipation. In this paper, we report an innovative bottom-up Cu electroplating technique with a high-aspect-ratio (10:1) through-diamond vias (TDV). The TDV structure was fabricated by laser processing. The electrolyte wettability of the diamond and metallization surface was improved by Ar/O plasma treatment. Finally, a Cu-filled high-aspect-ratio TDV was realized based on the bottom-up Cu electroplating process at a current density of 0.3 ASD. The average single-via resistance was ≤50 mΩ, which demonstrates the promising application of the fabricated TDV in the thermal management of advanced packaging systems.

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Section: Resultsmentioning

confidence: 99%

“…Advanced 3D integration methods based on Si chips presently include the preparation of TSVs, Cu filling, and hybrid bonding [ 15 , 16 ]. However, few reports have considered the integration of diamonds in 3D-IC.…”

Section: Introductionmentioning

confidence: 99%

Bottom-Up Cu Filling of High-Aspect-Ratio through-Diamond vias for 3D Integration in Thermal Management

Zhao

Wei

et al. 2023

Micromachines

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“…From Fig. 11, it is clear that a high thermal resistance value is preferred, which is the opposite of typical 3D (EIC) die stacks in which a good thermal contact is preferred 20 …”

Section: Mitigation Strategiesmentioning

confidence: 92%

“…11, it is clear that a high thermal resistance value is preferred, which is the opposite of typical 3D (EIC) die stacks in which a good thermal contact is preferred. 20 Fig. 10 (a), (b) Simulated thermal crosstalk for the reference case (test setup) and for a real package case (top-side cold plate).…”

Section: Mitigation Strategiesmentioning

confidence: 99%

Thermal modeling of hybrid three-dimensional integrated, ring-based silicon photonic–electronic transceivers

Coenen,

Kim,

Oprins

et al. 2023

J. Optical Microsystems

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Co-packaged optics for high performance computing or other data center applications requires dense integration of silicon photonic integrated circuits (PICs) with electronic integrated circuits (EICs). This work discusses the impact of three-dimensional (3D) hybrid integration on the thermal performance of Si ring-based photonic devices in wavelength-division multiplexing PICs. A thermal finite element model of the EIC-PIC assembly is developed and calibrated with thermo-optic device measurements, before and after integration of an electrical driver on top of the PIC by means of microbump flip-chip bonding. Both measurements and simulations of the thermal tuning efficiency and crosstalk between silicon photonic devices show that the EIC can have a significant impact on the thermal performance of the integrated heaters in the PIC by acting as an undesired heat spreader. This heat spreading lowers the heater efficiency with 43.3% and increases the thermal crosstalk between the devices by up to 44.4% compared with a PIC-only case. Finally, it is shown that these negative thermal effects of 3D integration can largely be mitigated by a thermally aware design of the microbump array and the back-end-of-line interconnect, guided by the calibrated thermal simulation model.

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“…The existing packaging process was executed by die thinning first and then bonding on a substrate. This process is difficult to control when the intermediate die becomes thinner to a certain level during die bonding, resulting in a defect in the suction step of lifting the die [7][8][9]. In addition, this method is limited because the size of the die varies for heterogeneously integrated packaging.…”

Section: Introductionmentioning

confidence: 99%

Die level thinning after bonding on the substrate in 3D packaging

Wang

Hu²,

Xiao³

et al. 2023

J. Phys.: Conf. Ser.

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This paper aims to realize heterogeneous integrated packaging technology for high integration by applying a thinning process technology for controlling the thickness of chipsets used in packaging, i.e., A technology for processing silicon dies with a thickness of 100 um or less and a technology for handling thinning ultrasmall dies. We combine wet etching with dry etching to fit an effective and practical experimental plan. Anisotropic etching in KOH solutions and ICP etching of silicon die bonding on a glass substrate are investigated. Die with copper wiring is fabricated and pasted on the substrate to achieve selective etching of the whole device. The topography of the die surface and corner is analyzed to prevent the influence on the second layer stacking process.

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3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding

Cited by 16 publications

References 23 publications

Bottom-Up Cu Filling of High-Aspect-Ratio through-Diamond vias for 3D Integration in Thermal Management

Bottom-Up Cu Filling of High-Aspect-Ratio through-Diamond vias for 3D Integration in Thermal Management

Thermal modeling of hybrid three-dimensional integrated, ring-based silicon photonic–electronic transceivers

Die level thinning after bonding on the substrate in 3D packaging

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