Standard NiAu/SAC (SnAgCu) solder bumps are compared with Cu pillar bumps in terms of their electromigration behavior. Both bump configurations are flip chipped onto package substrates with a thick Cu finish. The Cu pillar bumps, which are soldered with a thin SnAg cap, outperform the standard solder flip chip bumps due to the fast formation of an intermetallic phase which covers the full solder stand-off height. These bumps do not show any significant electromigration damage and do not fail within reasonable testing times and test conditions. For the standard solder flip chip bumps, micro-structural degradation at the NiAu chip metallization coincides with an according bump resistance increase which can be clearly monitored for all different test conditions. The electromigration parameters are calculated to be 0.90eV for the activation energy Q and 1.69 for the current density exponential factor n.A TaN temperature sensor is incorporated in the test chip which allows in-situ measurements of the actual device temperature. This value may deviate from the ambient temperature due to Joule heating. Fuse tests in which the current is gradually ramped up to a maximum of 3A while the resulting temperature rise is simultaneously monitored, are performed. In general, the thermal performance of the pillar bump exceeds the one of the solder bump.

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In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die–die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.

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