Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding

Abstract

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die–die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.

Influence of Composition of SiCN as Interfacial Layer on Plasma Activated Direct Bonding

“…Two different integration approaches of surface activated bonding have been mainly investigated for CMOS devices, one is dielectric bonding with via-last through-Si via (TSV) and another is Cu/dielectric hybrid bonding integration. 1,[7][8][9][10][11][12][13] For the case of dielectric bonding with via-last TSV integration, one of the requirements is to reduce its thermal budget while maintaining the bonding strength. In the hybrid bonding approach, the bonding interface consists of a dielectric layer and Cu metal pads, which are formed by a conventional Cu damascene process.…”

Sequential plasma activation methods for hydrophilic direct bonding at sub-200 °C

“…The bond energy can be calculated as G = 2γ = dE, where d is the number of interfacial bonds and E the bond energies of Si-O or Si-N bonds. 20) The bond energy of 2.7 J=m 2 implies that the number of interfacial bonds can be 3.7-3.8 per nm 2 . Assuming that the increase in bond energy from 1.4 J=m 2 (corresponding to a number of Si-OH of 2.0 per nm 2 ) to 2.7 J=m 2 is attributable to the additional ¸Si 2 -Ndangling bonds, the number of the ¸Si 2 -Ndangling bonds created by the N radical activation can be estimated to be at least 1.8 per nm 2 .…”

“…20) The bond energy of 2.7 J=m 2 implies that the number of interfacial bonds can be 3.7-3.8 per nm 2 . Assuming that the increase in bond energy from 1.4 J=m 2 (corresponding to a number of Si-OH of 2.0 per nm 2 ) to 2.7 J=m 2 is attributable to the additional ¸Si 2 -Ndangling bonds, the number of the ¸Si 2 -Ndangling bonds created by the N radical activation can be estimated to be at least 1.8 per nm 2 . Because the bonded interface may have nano-gaps owing to the nano-asperities on the mating surfaces, the actual number of bonding sites may be even greater.…”

“…Low-temperature wafer bonding is a useful technique for many applications such as three-dimensional integrated circuit (3D IC), 1,2) heterogeneous integration, [3][4][5] microelectro-mechanical systems (MEMS), 6) photonics=optics, 7) and microfluidics. [8][9][10][11] Many bonding techniques including indirect bonding and direct bonding have been developed for different applications.…”

Influence of Composition of SiCN Film for Surface Activated Bonding

“…Although a lot of wafer bonding methods are historically investigated [1][2][3][4][5][6], surface activated bonding is one of the most promising method to implement into CMOS process because of the high-compatibility including its low thermal budget. Two different surface activated bonding integration approaches have been mainly investigated for CMOS devices, one is dielectric bonding with via-last through-Si via (TSV) integration and the other is Cu/dielectric hybrid bonding [1,[7][8][9][10][11][12][13]. For the case of dielectric bonding with via last integration, one of the requirement is to reduce its thermal budget with maintaining the interfacial strength.…”