4-kV 100-Mbps monolithic isolator on SOI with multi-trench isolation for wideband network

Hashimoto, Takayuki; Yuyama, Y.; Amishiro, M.; Nemoto, M.; Yukutake, S.; Kojima, Yasuyuki; Kanekawa, Nobuyasu; Takeuchi, Yukiko; Watanebe, A.

doi:10.1109/ispsd.2009.5157998

Cited by 3 publications

(7 citation statements)

References 5 publications

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“…In this work, we proposed a unified impedance model that can express a general multiple trench gap structure. We confirmed that the unified impedance model expresses experimental results [30][31][32][33][34] and could lead to two effective approaches to improving the breakdown voltage analytically.…”

Section: Discussionsupporting

confidence: 68%

“…Figure 2(b) is a photograph of the isolator chip. [30][31][32][33][34] Analog circuits are shown in the left region and the digital circuit is in the right region.…”

Section: Isolation Structure and Issuementioning

confidence: 99%

“…However, the breakdown voltage between regions 1 and 2 was 1.5 kV ac . [30][31][32][33][34] This result is supposed to originate from the complexity of the multiple-trench-gap structure. The objectives of this work are to analyze this isolation structure, understand the differences between the expected and experimental results, and show a theoretical guideline for improvement.…”

Section: Isolation Structure and Issuementioning

confidence: 99%

“…They are the basic multiple-trench-gap, poly-Si based, and spiral-layout-type structures. 33,34) Considering the DC leakage path regions 1 and 2, impedance is an important element. Therefore, we introduced an impedance model composed of capacitance and resistance in multiple-trench-gap electrical models.…”

Section: Impedance Model and Analysismentioning

confidence: 99%

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Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

Takeuchi¹,

Kuroda²,

Sugawa³

2015

Jpn. J. Appl. Phys.

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We analyzed the shared voltages of multiple trench gaps on a silicon-on-insulator (SOI) substrate and showed the conditions for improving the breakdown voltage surrounded by these isolated structures. We introduced a unified impedance model instead of the capacitive model of trench gaps and determined the effective conditions for improving the breakdown voltage. The first condition is to reduce the impedance of trench gaps. In this case, the leak current gives a low limit of trench gap resistance. The second condition is to increase the substrate resistance. As silicon substrate resistance is not very high, this condition is not useful for the silicon substrate, but for other materials such as ceramics. We confirmed the effectiveness of these conditions from the simulation and experimental results of a fabricated chip.

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Section: Discussionsupporting

confidence: 68%

“…Figure 2(b) is a photograph of the isolator chip. [30][31][32][33][34] Analog circuits are shown in the left region and the digital circuit is in the right region.…”

Section: Isolation Structure and Issuementioning

confidence: 99%

Section: Isolation Structure and Issuementioning

confidence: 99%

Section: Impedance Model and Analysismentioning

confidence: 99%

See 2 more Smart Citations

Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

Takeuchi¹,

Kuroda²,

Sugawa³

2015

Jpn. J. Appl. Phys.

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“…On-chip isolation technology is one of the most adequate approaches for realizing these requirements [15][16][17] and several on-chip isolation devices with a multi trench isolation structure have been reported. [18][19][20][21][22][23][24][25] Figure 2 shows a review status of multi trench gap isolation structures. [18][19][20][21][22][23][24][25] As for the basic structure (1), isolation resistance is very high, but breakdown voltage is very low, because the applied voltage over the multi trench isolation is not evenly shared by the parasitic capacitors existing in between siliconon-insulator (SOI) and a substrate.…”

Section: Introductionmentioning

confidence: 99%

Analysis and reduction of leakage current of 2 kV monolithic isolator with wide trench spiral isolation structure

Takeuchi¹,

Kuroda²,

Sugawa³

2016

Jpn. J. Appl. Phys.

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In this work, the origin of the leakage current of a highly area-efficient silicon-on-insulator (SOI) monolithic isolator using a spiral trench isolation structure is clarified by experimental and simulation analyses and its reduction method is proposed. It was found that parasitic MOSFET inversion and accumulation channels formed at the SOI and buried oxide (BOX) interface are the origins of leakage current. To reduce the leakage current, adequate SOI spiral length and width and BOX layer thickness are proposed for various voltage usages and show the possibility of 4 kV voltage tolerance and 500 MΩ isolation resistivity.

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A Fully Integrated 0.6 Gbps Data Communication System for Inductive-Based Digital Isolator with 0.8 ns Propagation Delay and 10−15 BER

et al. 2023

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Digital isolators are implemented to protect low-voltage electronics and ensure human safety during high-voltage surge events. In this work, we present the design of an inductive-based digital isolation system that can sustain up to 1 kVrms breakdown voltage. The proposed system is designed using the pulse polarity modulation scheme and fabricated in a 0.35 μm CMOS. Two identical dies are bounded within the IC package, with one die housing the transmitter (Tx) and the isolation transformer, while the other die contains the receiver (Rx). Two different customized designs between three metal layers are implemented to form the isolation element. The transformer’s secondary coil is constructed in metal-1, while the primary coil is formed in metal-2 and metal-3 for comparing the system functionality, isolation capability, and propagation delay. The functionality has been verified by measurements for an operating frequency of 300 MHz with a 2.6 ns propagation delay and an energy consumption of 8.15 × 103 pJ/bit at 1 Mbps. The chip was tested under extreme temperatures and achieved a maximum measured common mode transient immunity (CMTI) of 500 V/μs. Jitter has been examined to ensure fast transmission at a bit error rate (BER) of 10−15 with a total jitter (TJ) of 188.18 ps.

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4-kV 100-Mbps monolithic isolator on SOI with multi-trench isolation for wideband network

Cited by 3 publications

References 5 publications

Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

Analysis and reduction of leakage current of 2 kV monolithic isolator with wide trench spiral isolation structure

A Fully Integrated 0.6 Gbps Data Communication System for Inductive-Based Digital Isolator with 0.8 ns Propagation Delay and 10−15 BER

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