40 Gbit/s optical receiver module with high conversion gain and sensitivity

A time-division-multiplexing (TDM) system transceiver with 4–channel 10 Gb/s interfaces to achieve 40 Gb/s non-return to zero (NRZ) transmission is presented. The front-end components are implemented in an indium phosphide double hetero-junction bipolar transistor (InP DHBT) technology. They include a 4:1 multiplexer with a voltage controlled oscillator and clock multiplication unit, modulator drivers for electro-absorption and differential lithium-niobate modulators, trans-impedance amplifier, limiting amplifier and 1:4 demultiplexer with clock and data recovery circuit. The transceiver was used to teat optical transmission over a 2.26 km link with a 40 Gb/s, 231-1 pseudo-random bit sequence (PRBS) data. The transmitter achieves better than 12.9 dB extinction ratio, 1 ps added root mean square (RMS) jitter and 4 dBm output power. Without any optical amplification the receiver achieves -9.1 dBm back to back sensitivity at a bit error rate (BER) of 10-12 and a high dynamic range of 12.5 dBm.

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“…The integrated receiver package 21 containing the PIN, TIA and LA incorporates a DC restoration loop ( fig. 24).…”

Section: Receivementioning

confidence: 99%

40 Gb/s TDM SYSTEM TRANSCEIVER PROTOTYPE IN InP HBT TECHNOLOGY

Krishnamurthy

Shou

Vetury

et al. 2005

Int. J. Hi. Spe. Ele. Syst.

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“…Since their optical/electrical bandwidth and conversion gain dominate the entire characteristics of the receivers [6], improving these crucial parameters are paramount in high data rate capability of the optical systems. For photoreceiver circuits' implementations, HEMTs [3,[5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, a surface illuminated, low-cost HBT-PIN-based OEICs receiver is undeniably important for high-performance 10 Gb/s EPON optical transmission system. [3,5,6,[9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24] This work is concerned with the design, characterisation and modelling of high-speed InP/InGaAs PIN-SHBT-based OEIC photoreceivers. More importantly, full-scale characterisations of the receivers using CAD tools prior to the fabricated circuits are invaluable in the prediction of prospective performances and to aid in further optimisations.…”

Section: Introductionmentioning

confidence: 99%

Low‐cost InP–InGaAs PIN–HBT‐based OEIC for up to 20 Gb/s optical communication systems

Muttlak

Kostakis²,

Abdulwahid

et al. 2019

IET Optoelectronics

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A detailed study of the performance analysis of a low cost PIN/HBT optoelectronic integrated circuit is described. Measured and of 54 and 57GHz for 10×10µm 2 HBTs were achieved for such a large emitter size. The base and collector regions of the transistor were utilized to form a PIN photodiode which has a dc responsivity and quantum efficiency of 0.5 A/W and 0.45 respectively without antireflection coating at a wavelength of 1.55µm. For both active devices, a model was realized taking all parasitic and physical-based impacts into account, for example equivalent circuit of the pads surrounding the devices and transit delay time across the collector depletion region. The simulation results of the discrete passive and active elements showed good agreement with experimental measurements. The OEIC module was implemented in Keysight-advanced design system software with a three stage preamplifier which has a transimpedance gain of 40dBΩ and a-3dB bandwidth of 18GHz. This corresponds to a transimpedance-gain product of 1.8THz. A series peaking inductor technique was used in the design, contributing to an enhancement in the opto-electrical bandwidth of >60%. The optical/electrical response offers a bandwidth of ~15GHz, adequate for up to 20 Gb/s data rate operation.

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“…In an optical interconnect, the receiver is a key component affecting the whole system performance in terms of speed, noise, sensitivity, and power consumption. Several achievements at high data rate operation (gigabit) have been obtained using III‐V materials and technologies such as InP, HEMT, GaAs, and Bi‐CMOS [2, 3]. However, the drawbacks of the III‐V material based chips are high power consumption and difficulty in integrating with other system chips based on CMOS technology.…”

Section: Introductionmentioning

confidence: 99%