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Abstract-This paper describes the design methodology of latches with three stable operating points. Open-loop analysis is used to obtain insight into how a conventional binary latch structure can be modified to yield a ternary latch. Four novel ternary latch structures, compatible with a standard CMOS process, are presented. Properties of each latch, including robustness of the ternary behavior, speed, and power dissipation, are described. Measurement results of four RS ternary flip-flops based on the proposed latch structures, fabricated in a standard 0.18-m CMOS process, are presented. Maximum operating frequency and skew tolerance are reported for each of the four latches.Index Terms-CMOS digital integrated circuits, CMOS memory circuits, digital integrated circuits, integrated logic circuits, multivalued logic circuits.

A time-division-multiplexing (TDM) system transceiver with 4–channel 10 Gb/s interfaces to achieve 40 Gb/s non-return to zero (NRZ) transmission is presented. The front-end components are implemented in an indium phosphide double hetero-junction bipolar transistor (InP DHBT) technology. They include a 4:1 multiplexer with a voltage controlled oscillator and clock multiplication unit, modulator drivers for electro-absorption and differential lithium-niobate modulators, trans-impedance amplifier, limiting amplifier and 1:4 demultiplexer with clock and data recovery circuit. The transceiver was used to teat optical transmission over a 2.26 km link with a 40 Gb/s, 231-1 pseudo-random bit sequence (PRBS) data. The transmitter achieves better than 12.9 dB extinction ratio, 1 ps added root mean square (RMS) jitter and 4 dBm output power. Without any optical amplification the receiver achieves -9.1 dBm back to back sensitivity at a bit error rate (BER) of 10-12 and a high dynamic range of 12.5 dBm.

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