Design of CMOS Ternary Latches

Shou, Xiaoqiang; Kalantari, Nader; Green, M.M.

doi:10.1109/tcsi.2006.885697

Cited by 11 publications

(4 citation statements)

References 13 publications

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“…However, additional inputs have been required that increase the circuit complexity. The design of low power and energy-efficient ternary adder and subtractor circuits using CNTFETs is designed (Sharma and Kumre, 2019). These circuits surpass the other similar designs in terms of power consumption, mainly due to the low power transmission gate style used to realize the majority of the circuit.…”

Section: Introductionmentioning

confidence: 99%

“…Additionally, the arithmetic operations are carried out faster with the ternary logic. The design of ternary circuits using complementary metal oxide semiconductor (CMOS) logic can be found in the literature (Shou et al, 2006) and (Shin et al, 2015). The performance comparison between the binary and ternary circuits has been studied in (Raychowdhury and Roy, 2005), more than 50% improvement has been observed in ternary logic circuits in terms of power consumption and chip area.…”

Section: Introductionmentioning

confidence: 99%

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Design of ternary subtractor using multiplexers

Kolanti¹,

Patel²

2021

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Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design of ternary subtractor using multiplexers

Kolanti¹,

Patel²

2021

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“…Thus, the ternary logic provides better performance over the binary logic. The design and implementation of ternary logic circuits using CMOS transistors are presented in Shou et al 23 The design of multithreshold devices is possible in CMOS using the body bias effect. However, during the fabrication process, providing various bias voltage to body terminals of MOS transistor is very challenging and mostly elusive.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk reduction in copper on‐chip interconnects with graphene barrier for ternary logic applications

Madhuri

Sunithamani

2020

Circuit Theory & Apps

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This paper presents the investigations of crosstalk effects in ternary logic-based coupled interconnects. The crosstalk analysis is investigated for coupled copper interconnects and copper-multilayer graphene (Cu-MLG) interconnects. In Cu-MLG interconnects, the Cu interconnect is enclosed with MLG barrier and standard ternary inverter is used to drive the interconnect. Based on the industry standard HSPICE simulation results, the crosstalk effects such as noise peak and delay are lower compared with conventional Cu interconnects. Moreover, the Cu-MLG interconnects show reduced power dissipation, power delay product (PDP), and energy delay product (EDP) over the Cu interconnects. From the simulation results, it is observed that the Cu-MLG interconnects provides the performance improvements up to 30.67% compared with the Cu interconnects. Thus, the Cu-MLG interconnects are more compatible for ternary logic integrated circuits compared with traditional Cu interconnects.

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“…And what is most important is that the most recent studies are based on binary logic system [6]- [9]. We know that the ternary logic system has lots of advantages than the binary logic system, especially in delays and power consumption [10]- [12]. But there are only a few studies work for comparators based on ternary logic system in recent years.…”

Section: Introductionmentioning

confidence: 99%

Ternary Logic Dynamic CMOS Comparators

Jin

Liu

et al. 2011

AMR

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In this paper, a new method of ternary logic circuit design is developed. It’s proposed that two types of static ternary CMOS comparators and three types of dynamic CMOS comparators, designed by new method, with low transistor count, high speed and low power consumption. The proposed comparators are the rearrangement and reordering of transistors in the evaluation block of a dynamic cell. These ternary comparators can be used as equality comparators, mutual comparators and zero/one/two detectors, which are widely used in build in self test and memory testing.

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Design of CMOS Ternary Latches

Cited by 11 publications

References 13 publications

Design of ternary subtractor using multiplexers

Design of ternary subtractor using multiplexers

Crosstalk reduction in copper on‐chip interconnects with graphene barrier for ternary logic applications

Ternary Logic Dynamic CMOS Comparators

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