40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170 $^{\circ}$C

Kimura, Takashi; Ito, Takashi; Tsuruda, Tamaki; Nishiyama, Tomohiro; Nagasawa, Tsutomu; Ogawa, Takahisa; Kawashima, Yasunaru; Hidaka, Hideto; Yamauchi, Takayoshi

doi:10.1109/jssc.2013.2280303

Cited by 35 publications

(15 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Low chip area has become a key design aspect for eFlash memories. Since the high voltage is supplied by onchip charge pump (CP) [2], the complicated operation voltage feature of eFlash memories [1,3] requires large area penalty of CP. Several designs of charge pump targeting smaller size and higher output capability have been proposed [3,4,5,6].…”

Section: Introductionmentioning

confidence: 99%

“…Since the high voltage is supplied by onchip charge pump (CP) [2], the complicated operation voltage feature of eFlash memories [1,3] requires large area penalty of CP. Several designs of charge pump targeting smaller size and higher output capability have been proposed [3,4,5,6]. The issues of output ripple [4] and gate-oxide reliability [5] may become significant, or extra power dissipation, area occupation [6] and uneconomical process integration [3] are produced.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Area-efficient charge pump with local boost technique for embedded flash memory

Zhu

Jun

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

An area-efficient charge pump (AE-CP) used for embedded flash memory is proposed with the combination of an area-efficient voltage doubler (AE-VD). An optimized strategy for AE-CP with local boost technique is discussed to maximize output capability by using low-voltage MOS capacitors together. The proposed circuits are simulated in a 130 nm CMOS process. Simulation results show the proposed AE-VD decreases the power consumption by 11.4%. And the proposed AE-CP with proposed voltage doubler achieves 29% improvement of the maximum output capability as compared to the conventional CP. A 253 × 8 KB embedded flash memory IP has been fabricated in HHGrace 130 nm 4 poly 4 metal CMOS process. The die size of the proposed IP is 0.65 mm 2 and the area size of charge pump has been reduced to 0.0317 mm 2 with an optimized α = 0.6 and the area ratio decreases by 10%.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Area-efficient charge pump with local boost technique for embedded flash memory

Zhu

Jun

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…In low-voltage based energy-efficient systems, volatile memory [5]- [9] is used for computing at a low supply voltage ( ), whereas embedded nonvolatile memory (eNVM) [10]- [13] is used for program and data storage in the power-off mode. The effective use of the power-off mode can enable relieving the power consumption of chips, as long as data can be backed up and stored reliably.…”

Section: Introductionmentioning

confidence: 99%

Low <formula formulatype="inline"><tex Notation="TeX">${\rm VDDmin}$</tex></formula> Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Chang

Chien

et al. 2015

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read-, and slow read access time ( ) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current ( ) resulting from the wide distribution of write (SET)-times ( ). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately greater sensing margin for lower and a faster read speed across a wide range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed tocut off the of devices with a rapid . The SBWT scheme reduces 99 of the with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved 404 ns when 0.27 V and confirmed the cutoff by the SBWT.Index Terms-ReRAM, RRAM, sense amplifier, voltage-mode sense amplifier, write driver. 0018-9200

show abstract

“…1, considerable savings can be achieved by using nonvolatile memory (NVM) to store program data in power-off mode [1]- [17] in conjunction with volatile memory, such as SRAM or DRAM [18]- [22], for computing in power-on mode. NAND-flash [23]- [25] is commonly used for off-chip storage and embedded Flash (eFlash) [26]- [28] can be found in on-chip NVM.…”

Section: Introductionmentioning

confidence: 99%

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Chang

Lee

Chen

et al. 2015

IEEE J. Emerg. Sel. Topics Circuits Syst.

View full text Add to dashboard Cite

Memristive devices have shown considerable promise for on-chip nonvolatile memory and computing circuits in energyefficient systems. However, this technology is limited with regard to speed, power, VDDmin, and yield due to process variation in transistors and memrisitive devices as well as the issue of read disturbance. This paper examines trends in the design of device and circuits for on-chip nonvolatile memory using memristive devices as well as the challenges faced by researchers in its further development. Several silicon-verified examples of circuitry are reviewed in this paper, including those aimed at high-speed, area-efficient, and low-voltage applications.Index Terms-Memristive device, memristor, nonvolatile memory, recent developments in resistive memory (ReRAM), resistive RAM.

show abstract

40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170 $^{\circ}$C

Cited by 35 publications

References 8 publications

Area-efficient charge pump with local boost technique for embedded flash memory

Area-efficient charge pump with local boost technique for embedded flash memory

Low <formula formulatype="inline"><tex Notation="TeX">${\rm VDDmin}$</tex></formula> Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Contact Info

Product

Resources

About