40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS

Kanda, Kensuke; Yamazaki, Daisuke; Yamamoto, Takuji; Horinaka, M.; Ogawa, J.; Tamura, Hirotaka; Onodera, Hidetoshi

doi:10.1109/isscc.2005.1493914

Cited by 52 publications

(29 citation statements)

References 4 publications

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“…We will discuss further about the feasibility of utilizing this idea on links which would require higher working frequencies if serialized. After checking the serial link designs in existing works [16,17], some conclusions are be reached. For example, for serial links working at frequencies higher than 3 GHz, current-mode logic (CML) is a better solution to enable the timing while for frequencies higher than 10 GHz, inductors need to be added into the design.…”

Section: Extension Studymentioning

confidence: 99%

“…The standard cell areas in a CML library designed in our laboratory are used for circuit designed at maximum 10 Gb/s. When inductive peaking technique is required, the MUX2:1 and DEMUX1:2 designed in [16] is borrowed because it has a more uniform structure, and ensures a more reliable system when cascaded into the rest part of the MUX/DEMUX link. The inductor size is also taken from 90 nm standard cell library.…”

Section: Extension Studymentioning

confidence: 99%

See 1 more Smart Citation

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

Sun

Cevrero

Athanasopoulos

et al. 2010

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip

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Abstract-This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis conducted in 90 nm CMOS technology shows that the proposed 2-Gb/s/pin quasi-serial link requires approximately five times less area than its parallel bus equivalent at same data rate for a TSV diameter of 20 μm.

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Section: Extension Studymentioning

confidence: 99%

Section: Extension Studymentioning

confidence: 99%

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

Sun

Cevrero

Athanasopoulos

et al. 2010

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip

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“…However, these process are costly and difficult to integrate with other CMOS blocks in SerDes systems. Multiplexers based on CMOS process have been presented at 10Gb/s data rate [4]- [5]. All of these multiplexers have 2 N input channels and can be implemented by traditional treetype topology but cannot be applied directly into 8B/10B SerDes transmitter.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power 12.5Gb/s 10:1 Multiplexer

Zhuo¹,

Feng²

2013

Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)

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Abstract-Design of a 10:1 multiplexer in 0.18µm CMOS technology is presented in this paper. This circuit can be used in 12.5Gb/s SerDes transmitter. The speed of traditional 10:1 is difficult to enhance due to the serial 5:1 part. In this paper, 5B/4B converter is adopted to convert the 10 channel data into 8 channel data and use tree type topology to increase the speed and save the power consumption in the data path. At the same time, phase switching divider is used to decrease the power consumption in the clock path. The core area occupies 800µm*500µm. The post simulation results show that the multiplexer can operate correctly at 12.5Gb/s, the power consumption is less than 125mW, the single-ended output peak-to-peak value is 200mV and the output jitter is less than 0.1UI.

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“…The latches Ldo and Ld2 align the outputs from the lower 1:2 DEMUX with those from the upper one. The 1:4 DEMUX uses 12 latches altogether, as opposed to 15 in the conventional tree architecture [3], [4], which uses three 1:2 DEMUXes operating at a half rate. The quarterrate operation of the 1:2 DEMUXes in our design leads to low power dissipation.…”

Section: Introductionmentioning

confidence: 99%

“…2(a). The current-sourceless CML structure was recently proposed for low-voltage operation [4], [7]. The tail transistor is eliminated to give increased voltage headroom.…”

Section: Introductionmentioning

confidence: 99%

A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process

Mineyama

Suzuki

Ito

et al. 2009

2009 International Microwave Workshop Series on Signal Integrity and High-Speed Interconnects

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A 9.5 mW 20 Gb/s 40 x 70 /_m2 inductorless 1:4 DEMUX in 90 nm CMOS process is presented. In order to reduce power and area, the DEMUX uses a multi-phase clock architecture that requires a smaller number of latches operating at a slower clock rate than in the conventional tree architecture. To provide low-voltage scalability, the latches operate with a near-tail-to-rail logic swing. It is realized without significant speed penalty by adopting current-sourceless CML-type latches with unconventional settings. It offers a larger noise margin and elimination of logic level converters too. The well-balanced scalable design could possibly broaden the applications of high-speed SerDes in the coming ultralowvoltage many-core era.Index Terms -DEMUX, CMOS, multi-phase clock architecture, near-rail-to-rail logic swing I. INTRODUCTION Applications of high-performance demultiplexers (DEMUXes) [1]-[6] have so far been limited chiefly to those that accept a design trade-off in favor of speed, such as fiberoptic communication systems. In typical optical wavelengthdivision multiplexing (WDM) systems, for example, perwavelength speed of 10 Gb/s or faster is required. The conventional wisdom in gaining or maintaining speed of CML-type circuits, used in [1]-[6], has been to reduce the signal amplitude. A dilemma here is that the noise immunity might have to be traded off. Another problem is that current-mode logic (CML)-type circuits do not go well with the trend of lowering the supply voltage. As regards other factors than the speed, since as many DEMUXes as the wavelength multiplicity are needed in WDM systems, the power and area are also important considerations. We present a 1:4 DEMUX with near-rail-to-rail architecture that could offer a possible solution to the challenges in signal integrity and low-voltage scalability as well as in balancing the speed, power, and area.

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40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS

Cited by 52 publications

References 4 publications

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

Design of Low Power 12.5Gb/s 10:1 Multiplexer

A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process

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