450 mm Silicon: An Opportunity and Wafer Scaling

Watanabe, Masaharu; Kramer, Scott

doi:10.1149/2.f04064if

Cited by 23 publications

(6 citation statements)

References 5 publications

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“…As shown in Fig. 13, in a larger, 450 mm diameter wafer, 31) inherent radial unevenness naturally increases. The center of a wafer being polished has a higher temperature than the edge regions.…”

Section: Starting Materialmentioning

confidence: 95%

The way to zeros: The future of semiconductor device and chemical mechanical polishing technologies

Tsujimura

2016

Jpn. J. Appl. Phys.

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For the last 60 years, the development of cutting-edge semiconductor devices has strongly emphasized scaling; the effort to scale down current CMOS devices may well achieve the target of 5 nm nodes by 2020. Planarization by chemical mechanical polishing (CMP), is one technology essential for supporting scaling. This paper summarizes the history of CMP transitions in the planarization process as well as the changing degree of planarity required, and, finally, introduces innovative technologies to meet the requirements. The use of CMP was triggered by the replacement of local oxidation of silicon (LOCOS) as the element isolation technology by shallow trench isolation (STI) in the 1980s. Then, CMP’s use expanded to improving embedability of aluminum wiring, tungsten (W) contacts, Cu wiring, and, more recently, to its adoption in high-k metal gate (HKMG) and FinFET (FF) processes. Initially, the required degree of planarity was 50 nm, but now 0 nm is required. Further, zero defects on a post-CMP wafer is now the goal, and it is possible that zero psi CMP loading pressure will be required going forward. Soon, it seems, everything will have to be “zero” and perfect. Although the process is also chemical in nature, the CMP process is actually mechanical with a load added using slurry particles several tens of nm in diameter. Zero load in the loading process, zero nm planarity with no trace of processing, and zero residual foreign material, including the very slurry particles used in the process, are all required. This article will provide an overview of how to achieve these new requirements and what technologies should be employed.

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Section: Starting Materialmentioning

confidence: 95%

The way to zeros: The future of semiconductor device and chemical mechanical polishing technologies

Tsujimura

2016

Jpn. J. Appl. Phys.

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“…As research in CCP PECVD continues, economic concerns are promoting the advancement of CCP PECVD by using larger substrates (e.g. the wafer diameter for recent semiconductor production needed to be increased up to 450 mm [12]) and hence larger reactors because the enormous success of the semiconductor industry in recent years has motivated a constant reduction in production costs. In addition, as the density of semiconductor devices has increased, the development of thin-film transistor technologies has led to challenging specifications for the extreme uniformity of thin-film thickness.…”

Section: Introductionmentioning

confidence: 99%

Numerical analysis of the effect of electrode spacing on deposition rate profiles in a capacitively coupled plasma reactor

Kim

Lee

2016

Plasma Sources Sci. Technol.

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The effect of reactor dimension on deposition rate profiles is analyzed with a two-dimensional (2D) fluid simulation of a capacitively coupled plasma (CCP) reactor to deposit a hydrogenated silicon nitride (SiN x H y ) film with a SiH 4 /NH 3 /N 2 /He gas mixture. We focus on the complex function of electrode spacing to reveal the physical relation between reactor geometry and deposition rate profiles. The simulation demonstrates that the localization of electron density is concentrated close to the powered electrode periphery for electrode spacing of 9 mm. However, the plasma distribution becomes bulk dominated with electrode spacing of 15 mm by relaxing the localization. As a result, the increase in the electrode spacing creates a more uniform electron power density profile, and the deposition rate profile of SiN x H y film changes from convex to concave in a radial direction. The change in the deposition rate profile is validated through comparison with the experimental observation, which agrees well with the simulation results with errors of less than 5%. The deposition rate profile with electrode spacing of 9 mm is very sensitive to the non-uniform gas density condition applied to the showerhead inlet. However, the deposition rate profile with electrode spacing of 15 mm is not sensitive to the inlet gas profile because of the increasing residence time. The increase of the electrode spacing promotes molecule-molecule gas phase reactions and consequently weakens the effect of the inlet boundary condition.

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“…Large and thin silicon substrates are widely used in the semiconductor and microelectronics industries to increase productivity and reduce cost [1,2], and to increase packaging density and enhance the performance [3][4][5]. Different methods including grinding with ultra-fine diamond wheels and chemical mechanical grinding have been used for machining silicon wafers in order to obtain ultra-smooth and ultrathin wafers [6,7].…”

Section: Introductionmentioning

confidence: 99%

A new method for measuring the flatness of large and thin silicon substrates using a liquid immersion technique

Liu

Dong

Huang

et al. 2015

Meas. Sci. Technol.

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Flatness measurements of thin and large substrates are greatly affected by gravity. In this work, a new method was proposed for accurately measuring the flatness error of large and thin silicon wafers using a floating technique. In this method, a silicon wafer was immersed in a liquid that had a density slightly lower than that of silicon and was supported by three ball supporters in the liquid. The wafer shape was measured using a laser triangulation sensor. The buoyancy force on the wafer inside the liquid could cancel out most of the effect of gravity. The residual effect of gravity was further removed by subtracting the residual deflection calculated by finite-element modeling from the measured result. The method was validated by comparing the flatness values of a thick wafer measured using this method and via a commercially available interferometer. The deformations of wafers ground by #600 and #2000 diamond wheels were measured and the measurement error was less than 3% of the total deformation.

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450 mm Silicon: An Opportunity and Wafer Scaling

Abstract: Today, we take our favorite music and movies anywhere. It is a result of the never-ending reduction in bit cost brought about by the accelerating development of semiconductor devices and their production technology.

Cited by 23 publications

References 5 publications

The way to zeros: The future of semiconductor device and chemical mechanical polishing technologies

The way to zeros: The future of semiconductor device and chemical mechanical polishing technologies

Numerical analysis of the effect of electrode spacing on deposition rate profiles in a capacitively coupled plasma reactor

A new method for measuring the flatness of large and thin silicon substrates using a liquid immersion technique

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