45nm CMOS 8&amp;#x03A9; Class-D audio driver with 79% efficiency and 100dB SNR

Samala, Sreekiran; Mishra, Vineet; Chakravarthi, Kalyan Chekuri

doi:10.1109/isscc.2010.5434036

Cited by 7 publications

(5 citation statements)

References 2 publications

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“…Table 1 resumes the performances of recently published amplifiers. [6] is a recent PWM based Class-D amplifier, using 45nm CMOS process (which explain the low power efficiency). [3,7] are two 1W PSSO Class-D dedicated to mobile phone.…”

Section: B Conducted and Emitted Emi Measurementmentioning

confidence: 99%

A synchronized self oscillating Class-D amplifier for mobile application

Cellier¹,

Nagari²,

Hacine³

et al. 2012

2012 Proceedings of the ESSCIRC (ESSCIRC)

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International audienceAn integrated Class-D amplifier using a synchronized self-oscillating modulator based on a hysteresis control is presented. This new feedback topology can achieve a higher gain bandwidth product to increase linearity and power supply rejection than the fixed switching frequency solutions. The switching frequency spread can also reduce the external EMI filtering constraints. To reduce the idle consumption and radiated emissions at zero output level, a synchronization technique is presented to provide truly differential outputs. The proposed amplifier, realized in CMOS 130nm process, drives up to 1W load with 0.02% THD+N, 90% efficiency with power supply range from 2.3 to 5V. The synchronization technique reduces shows up to 75% of idle consumption

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Section: B Conducted and Emitted Emi Measurementmentioning

confidence: 99%

A synchronized self oscillating Class-D amplifier for mobile application

Cellier¹,

Nagari²,

Hacine³

et al. 2012

2012 Proceedings of the ESSCIRC (ESSCIRC)

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“…Table 1 lists the summary of the CDA performance and its comparison with the state-of-the-art CDAs. Compared with the digital [31] and analog [32] CDAs, the proposed CDA presents a significant advantage of higher output power for 1%THD + N. It achieves lower THD + N compared with the analog [17,33] and digital [34] CDAs. Furthermore, it achieves higher efficiency than the others.…”

Section: Simulation Resultsmentioning

confidence: 99%

High-Fidelity and High-Efficiency Digital Class-D Audio Power Amplifier

Wei

et al. 2021

Journal of Electrical and Computer Engineering

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This study presents a high-fidelity and high-efficiency digital class-D audio power amplifier (CDA), which consists of digital and analog modules. To realize a compatible digital input, a fully digital audio digital-to-analog converter (DAC) is implemented on MATLAB and Xilinx System Generator, which consists of a 16x interpolation filter, a fourth-order four-bit quantized delta-sigma (ΔΣ) modulator, and a uniform-sampling pulse width modulator. The CDA utilizes the closed-loop negative feedback and loop-filtering technologies to minimize distortion. The audio DAC, which is based on a field-programmable gate array, consumes 0.128 W and uses 7100 LUTs, which achieves 11.2% of the resource utilization rate. The analog module is fabricated in a 0.18 µm BCD technology. The postlayout simulation results show that the CDA delivers an output power of 1 W with 93.3% efficiency to a 4 Ω speaker and achieves 0.0138% of the total harmonic distortion (THD) with a transient noise for a 1 kHz input sinusoidal test tone and 3.6 V supply. The output power reaches up to 2.73 W for 1% THD (with transient noise). The proposed amplifier occupies an active area of 1 mm2.

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“…The current copy is then divided by a factor K thanks to the drawn current mirrors. In principle the current sense could be done only with the lower resistors connected to ground as in [4][5], but there are a few advantages in doing the current copy with the four resistors as illustrated in figure 4: Figure 4: Schematic of 40nm Class-D power stage with fully integrated load current sensing (cascode devices has been omitted for simplicity).…”

Section: Load Current Sensingmentioning

confidence: 99%

“…The overall system, including PWM_DAC, loop filter and power stage has a quiescent current of 2.56mA with Vana = 2.2V; the dynamic cascode biasing reports a quiescent current saving of about 0.8mA with a negligible impact in the overall area and no effects on THD+N performance. Table I summarizes the overall performances showing the best quiescent current for a Class-D in sub-nm technology vs. [4][5][6]. …”

Section: Measurementsmentioning

confidence: 99%

“…At high output power, the weak point is the MOS resistivity (R DS-ON ), while at low output power or quiescent mode, the power losses are essentially due to capacitive switching loss. To fulfill high output power demand without compromising the reliability constraints, some architecture for the power stage design is available [4][5][6]: The second solution is often preferred to the extended drain, due to its non-additional mask and thus its reduced cost. One solution widely used to minimize consumption in low output power mode is to segment the power stage and power down some branches as illustrated in figure 2 (in this figure only the half bridge of a full H-bridge audio amplifier is reported).…”

Section: Introductionmentioning

confidence: 99%

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A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensing

Binet

Amiard

Allier

et al. 2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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To address in the same time high efficiency, high output power and high complexity functions for Signal Processing systems, the partitioning tends to integrate in the same chip some functions of the digital (like DSP) and audio amplifiers (like Class-D) in a deep submicron technology. To fulfill high output power demand without compromising the device's reliability constraints, the amplifier power-stage use cascoded structure. In this paper a new design aimed to decrease the power stage consumption adapting the cascode bias of power stage branches during its switching is presented without impacting the MOS device's reliability.In addition, a fully integrated load current sensing, independent from any process, package or temperature spread, suitable for Class-D speaker protection systems, is explained. The circuit has been implemented in 40nm CMOS technology.I.

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45nm CMOS 8Ω Class-D audio driver with 79% efficiency and 100dB SNR

Cited by 7 publications

References 2 publications

A synchronized self oscillating Class-D amplifier for mobile application

A synchronized self oscillating Class-D amplifier for mobile application

High-Fidelity and High-Efficiency Digital Class-D Audio Power Amplifier

A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensing

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