4K Real-Time HEVC Decoder on an FPGA

Abeydeera, Maleen; Karunaratne, Manupa; Karunaratne, Geethan; Silva, Kalana De; Pasqual, Ajith

doi:10.1109/tcsvt.2015.2469113

Cited by 44 publications

(19 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Low‐cost decoder architecture with primary and secondary reference buffer which can perform palette decoding and intra block copy is proposed in Zhou et al It has four pipeline stages with four static SRAMs of sizes 3, 4, 16.5, and 24 K bytes memory, respectively. A high efficiency elastic pipelined video coding decoder for absorbing processing variations is implemented in Abeydeera et al In this work, an operating frequency of 150 MHz is achieved by managing critical path delays and with a few novelties in architecture like deblocking filter, offset filter, and transformed coefficient matrix etc. A pipelined LDPC decoder for WiMax is designed in Andrade et al It includes many single instruction configurations combined together for increasing parallelism which in turn gives additional throughput, precision, and bit error rate performance.…”

Section: Overview Of Conventional Techniques For Viterbi Decodermentioning

confidence: 99%

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Radha

Shylu

Nagabushanam

2019

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary Viterbi decoder (VD) is the majority used decoder for convolutional codes which play a role in WLAN and WSN applications. The trellis in VD needs proper analysis to calculate the metric at each stage to obtain a shortest path from every state to the next state. Existing techniques in VD design are namely (a) pipelined architecture, (b) modular ACS and buffers technique, and (c) quasi cyclic trellis technique. The key challenge of the VD trellis circuit is to attain high throughput and better latency performance with low power consumption without affecting hardware complexity of VD. This paper presents several of conventional methods used in VD. We also proposed a new method for VD with K the constraint length as multiple of M, the radix in trellis to calculate the shortest survival path to travel in trellis. The proposed VD is simulated using Xilinx. Use of a trace back approach in the proposed Viterbi decoder with capacitive and resistive feedback yields better throughput, latency, and power consumption with respect to other techniques. The static power outputs obtained in RE, shift update, and selective update methods using Libero IDE are also compared.

show abstract

Section: Overview Of Conventional Techniques For Viterbi Decodermentioning

confidence: 99%

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Radha

Shylu

Nagabushanam

2019

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…Frames per second performance of the HEVC intra prediction hardware proposed in [12] is not reported. Since the HEVC intra prediction hardware in [10] is proposed for an HEVC decoder, its frames per second performance for an HEVC encoder is not reported. …”

Section: Proposed Hevc Intra Prediction Hardwarementioning

confidence: 99%

An efficient FPGA implementation of HEVC intra prediction

Azgın

Mert

Kalalı

et al. 2018

2018 IEEE International Conference on Consumer Electronics (ICCE)

View full text Add to dashboard Cite

Abstract-Intra prediction algorithm used in High EfficiencyVideo Coding (HEVC) standard has very high computational complexity. In this paper, an efficient FPGA implementation of HEVC intra prediction is proposed for 4x4, 8x8, 16x16 and 32x32 angular prediction modes. In the proposed FPGA implementation, one intra angular prediction equation is implemented using one DSP block in FPGA. The proposed FPGA implementation, in the worst case, can process 55 Full HD (1920x1080) video frames per second. It has up to 34.66% less energy consumption than the original FPGA implementation of HEVC intra prediction. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.

show abstract

“…As the intra prediction of HEVC supports 35 prediction modes and various sizes of PU and processes the reference pixel smoothing process and the filtering process of the predicted pixel, the amount of computations and the computational complexity are greatly increased, compared to the existing H.264/AVC in implementation of the hardware [5]. Several architectures for hardware implementation of intra prediction in HEVC have been discussed in [6][7][8][9]. The architecture in [6] proposed a flexible reference sample selection technique and a register array to reduce memory resource.…”

Section: Introductionmentioning

confidence: 99%

“…The design in [7] adopts two pipelines to produce 4x4 pixel data with varied throughputs and a method to process reference pixel fetching and padding. The design in [8] proposed an efficient VLSI architecture to support 8Kx4K HEVC decoder and a cyclic SRAM banks based parallel reference sample fetching. The design consists of common operation unit for generating predicted pixels for all modes and reference pixel substitution unit to process reference substitution and smoothing.…”

Section: Introductionmentioning

confidence: 99%

A Low-Cost Complexity Intra Prediction Hardware Architecture for HEVC Decoder

2019

IJRTE

View full text Add to dashboard Cite

High Efficiency Video Coding (HEVC) adopts new techniques to reduce bit-rate by 50% over a previous video compression standard. The number of intra prediction modes in HEVC is 35 modes and increased compared with the compression. Therefore, hardware architecture with common equation and a fast filter coefficient generation algorithm is proposed for low complexity intra prediction hardware. The proposed architecture performs a smoothing filter, interpolation filter, generation of predicted pixels with only Common Operation Unit (COU). Various equations in intra prediction for smoothing filter of reference samples, calculating the average of the reference samples, generating predicted pixels and filtering predicted pixels is modified to one common equation. The common operation unit using a common equation in intra prediction hardware architecture reduces hardware area and the number of computational operators to perform various equations. COU uses 2 multipliers, 9 adders, 3 shifters and generates 1 predicted sample in planar mode and 2 predicted samples in the other mode. Also, COU generates 2 filtered reference samples in filtering operation of reference samples and the average of 4x4 PU in DC mode. The fast filter coefficient generation algorithm reduces processing time by using only Look-Up Table (LUT) and adders, instead of multiplying operation and the number of computational operators. The number of gates of the architecture is 45.6k. The number of gates in the proposed intra prediction hardware is 36.7% less than previous architecture.

show abstract

4K Real-Time HEVC Decoder on an FPGA

Cited by 44 publications

References 15 publications

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

An efficient FPGA implementation of HEVC intra prediction

A Low-Cost Complexity Intra Prediction Hardware Architecture for HEVC Decoder

Contact Info

Product

Resources

About