An efficient FPGA implementation of HEVC intra prediction

Azgın, Hasan; Mert, Ahmet Can; Kalalı, Ercan; Hamzaoğlu, İlker

doi:10.1109/icce.2018.8326332

Cited by 11 publications

(14 citation statements)

References 14 publications

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“…The symbols "×", "{ , }", "|", "≪" and "≫" represent multiplication, concatenation, bit-wise or, left shift and right shift operations, respectively. This method can be used for k constant multiplications if the bit lengths of input variable and constants satisfy the condition in (2).…”

Section: Proposed Methodsmentioning

confidence: 99%

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Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA

Mert

Azgın

Kalalı

et al. 2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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Multiple constant multiplication (MCM) operation multiplies an input variable with multiple constants. MCM operations are widely used in many applications such as video processing and compression. In this paper, a method is proposed for efficient implementation of MCM operations using DSP blocks in Xilinx FPGAs. The proposed method reduces number of DSP blocks used for implementing a given MCM operation by manipulating the multiple constants used in this MCM operation. In this paper, a high level synthesis tool implementing the proposed method is also proposed. The proposed tool takes the input variable bit length and multiple constants as inputs, and generates a Verilog RTL code which efficiently implements this MCM operation using DSP blocks. The proposed method and tool are used for one of the most complex video compression algorithms, HEVC 2D DCT. They reduced number of DSP blocks used in the FPGA implementation of HEVC 2D DCT algorithm by 35.8%.

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Section: Proposed Methodsmentioning

confidence: 99%

“…DSP blocks, which have full-custom multiplier hardware, are one of these built-in blocks in FPGAs. They are used in FPGA implementations of many applications such as video processing and compression, and machine learning [1]- [2].…”

Section: Introductionmentioning

confidence: 99%

Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA

Mert

Azgın

Kalalı

et al. 2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

Self Cite

View full text Add to dashboard Cite

show abstract

“…The whole time is in relation to a clock frequency that is equal to 143.65 MHz. Comparison our work on FPGA implementation of HEVC intra prediction with the proposed hardware on the FPGA in [21], it has less area and high frequency. however the performance the its architecture up to 55 frames per second only for resolution full HD against our up to real time processing for resolution 4K.…”

Section: Resources Analysismentioning

confidence: 99%

An energy-aware system-on-chip architecture for intra prediction in HEVC standard

Ansari¹,

Mansouri²,

Ahaitouf³

2019

IJECE

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<p>High resolution 4K and 8K are becoming the more used in video applications. Those resolutions are well supported in the new HEVC standard. Thus, embedded solutions such as development of dedicated ystems-On-Chips (SOC) to accelerate video processing on one chip instead of only software solutions are commendable. This paper proposes a novel parallel and high efficient hardware accelerator for the intra prediction block. This accelerator achieves a high-speed treatment due to pipelined processing units and parallel shaped architecture. The complexity of memory access is also reduced thanks to the proposed design with less increased power consumption. The implementation was performed on the 7 Series FPGA 28 nm technology resources on Zynq-7000 and results show, that the proposed architecture takes 16520 LUTs and can reach 143.65 MHz as a maximum frequency and it is able to support the throughput of 3840×2160 sequence at 90 frames per second.</p>

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“…An energy consumption reduction of 34.66% compared to the original HEVC intra prediction is reported in [14]. One DSP block in FPGA implemented one intra angular prediction.…”

Section: Related Workmentioning

confidence: 99%

“…One DSP block in FPGA implemented one intra angular prediction. The implementation could process HD video at 55 frames/seconds [14].…”

Section: Related Workmentioning

confidence: 99%

Code Improvements Towards Implementing HEVC Decoder

Israr

Nazir

Kaleem

2018

2018 3rd International Conference on Emerging Trends in Engineering, Sciences and Technology (ICEEST)

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HEVC is the latest video coding standard achieving better compression as compared to previous standards but at a higher complexity. Many applications require fast and real-time decoding of compressed video for which Field Programmable Gate Array (FPGA) is one of the efficient options. In this paper we provide the code improvement and implementation of the computationally intensive HEVC decoder. We describe our investigation for the implementation of HEVC decoder on Visual C++ 2008 platform and present improvements to the code of HEVC decoder required prior to its conversion to a hardware description language. The results for decoding time are also provided.

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An efficient FPGA implementation of HEVC intra prediction

Cited by 11 publications

References 14 publications

Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA

Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA

An energy-aware system-on-chip architecture for intra prediction in HEVC standard

Code Improvements Towards Implementing HEVC Decoder

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