5.4 GOPS linear array architecture DSP for video-format conversion

Kurokawa, M.; Hashiguchi, A.; Nakamura, Kazuyuki; Okuda, H.; Aoyama, K.; Yamazaki, Takao; Ohki, Mitsuharu; Soneda, Mitsuo; Seno, K.; Kumata, I.; Aikawa, Masatoshi; Hanaki, H.; Iwase, Seiichiro

doi:10.1109/isscc.1996.488594

Cited by 7 publications

(3 citation statements)

References 3 publications

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“…This paper presents a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with a 3D-stacked column parallel Analog-to-Digital Converter (ADC) [ 14 ] and 140 GOPS programmable SIMD column parallel PEs for diverse sensing applications [ 15 ]. The architecture of the parallel signal processor was developed as an image processing Digital Signal Processor (DSP) [ 16 , 17 , 18 ] and the technology of the processor is applied to the vision chip to realize high-speed sensing. The architecture of the parallel signal processor is like the column-based readout sensor architecture.…”

Section: Introductionmentioning

confidence: 99%

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †

Nose¹,

Yamazaki²,

Katayama³

et al. 2018

Sensors

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We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

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Section: Introductionmentioning

confidence: 99%

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †

Nose¹,

Yamazaki²,

Katayama³

et al. 2018

Sensors

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show abstract

“…The emerging "smart memory" [1][2][3][4][5][6][7][8][9][10][11][12] architecture gets speed by exploiting the internal datapath width in memory chips, and energy efficiency by keeping computations localized on a millimetre scale. These chips are best seen as memories that supplement the generality of more conventional computer architectures, offering excellent performance on the "massively-parallel component" of computations without attempting to handle the serial fraction.…”

Section: Introductionmentioning

confidence: 99%

“…Benchmark Speedups 7611. Acknowledgments MOSAID has hosted and supported this project for several years, and their staff have been generous in explaining the real-world constraints ofDRAM to us.…”

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confidence: 99%

<title>Computing RAMs for media processing</title>

Elliott

Snelgrove

Cojocaru³

et al. 1997

SPIE Proceedings

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Integrating processing elements in DRAM makes very large bus widths available: at least 2K processing elements fit in a 4Mb chip or 4K in a 16Mb DRAM. The processors can add an area overhead as low as 10% and power overhead of about 10-25%. To get these efficiencies, the processors have to be pitch-matched to the DRAM. Interprocessor communication is also severely limited, especially when going "off-chip" while retaining low-cost packaging. These "computing RAMs" (C.RAM) can form the main memory for SISD or MIMD hosts, making their contributions to the computing load scalable. The SIMD nature of C'RAM matches large image-processing tasks with high uniformity and locality ofreference, making real-time DCT, anti-aliasing and a variety of transformations available at the low cost required for consumer applications.Even given a PE "budget" of 70-200 transistors, and with the limited interconnect characteristic of low-cost DRAM, there are quite a few architectural choices available to the computer architect. These can be made to favour the data widths and operations needed for image processing while retaining good generality.

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A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing

Ikenaga

Ogura

2000

IEEE J. Solid-State Circuits

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5.4 GOPS linear array architecture DSP for video-format conversion

Cited by 7 publications

References 3 publications

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †

<title>Computing RAMs for media processing</title>

A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing

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