A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing

Towards a low search-energy nonvolatile ternary content-addressable memory (TCAM), we propose a novel nine-transistor/two-magnetic-tunnel-junction (9T–2MTJ) nonvolatile TCAM cell circuit with a high-speed accessibility. Since critical path for switching in the TCAM cell circuit is only a single metal-oxide-semiconductor (MOS) transistor, switching delay of the TCAM word circuit is minimized. As a result, the worst-case switching delay of 0.22 ns is achieved in a 144-bit word circuit under a 90 nm complementary MOS (CMOS)/MTJ technology, which is about 2.6 times faster than that of a conventional CMOS-based TCAM. In order to minimize the active power dissipation in the proposed TCAM, a multi-level segmented match-line scheme that maximally brings inessential cells to standby state is also applied to the 9T–2MTJ-cell-based word circuit. Finally, low search-energy of 0.73 fJ/bit/search is achieved in a 144-bit × 256-word nonvolatile TCAM together with eliminating standby power using nonvolatility.

Section: Introductionmentioning

confidence: 99%

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

Matsunaga

Katsumata

Natsui

et al. 2012

“…In this paper, we present a ternary content-addressable memory (TCAM) based on the MOS/nonvolatile-devicehybrid logic-in-memory architecture as a remarkable example of an ultra low-power circuit. The TCAM is a powerful data-searching hardware with parallel data processing capability, which can be used for a number of applications [14][15][16][17][18][19] such as network routers, fully parallel image processors, and central processing unit (CPU) caches. However, a conventional complementary MOS (CMOS)based TCAM tends to suffer from an area penalty, because bit-level logic operation as well as data storage must be performed in separated circuit cells.…”

Section: Introductionmentioning

confidence: 99%

Fine-Grained Power-Gating Scheme of a Metal–Oxide–Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory

Matsunaga

Natsui

Hiyama

et al. 2010

A fine-grained power-gating scheme combining metal–oxide–semiconductor (MOS) transistors with magnetic-tunnel-junction (MTJ) devices, where storage data still remains even if the power supply is cut off, is proposed for an ultra low-power bit-serial ternary content-addressable memory (TCAM). Once a mismatched result is detected in a sequence of a bit-level equality-search operation, the power supply of all the cells in the word circuit is cut off, which greatly reduces the standby power dissipation in the word circuit. The standby power dissipation of the proposed TCAM in the standby mode is reduced to about 1.2% in comparison with that of a complementary MOS (CMOS)-only-based TCAM. Moreover, the power-delay product of the proposed TCAM is reduced to 15.5% in comparison with that of the corresponding CMOS-only-based TCAM.

“…It can be used for a number of applications such as parallel image processors, data compression hardware, and central processing unit (CPU) caches. [1][2][3][4][5][6] However, a conventional complementary metal-oxide-semiconductor (CMOS)-based CAM tends to suffer from an area penalty since it must consist of a normal static random access memory (SRAM) cell (six transistors) to perform data storage function and additional logic circuit (three transistors at least) to perform equality-search operation. 7) Moreover, standby power dissipation due to leakage current in a CMOS-based cell circuit is increasingly dominating its power dissipation in recent nanometer-scaled technology.…”

Section: Introductionmentioning

confidence: 99%

Compact Integrated Folded Šolc Filter using Periodic 90°-Domain Structures in KNbO₃Single Crystals

Hirohashi¹,

Yamada²,

Kamio³

et al. 2004

A perpendicular magnetic tunnel junction (P-MTJ)-based one-transistor/one-resistor (1T-1R) binary content-addressable memory (CAM) is proposed for a high-density nonvolatile CAM. The proposed CAM cell performs an equality-search operation between an input bit and the corresponding stored bit by detecting the difference of a ''cell resistance'', where the cell resistance is determined by the series connection of one metal-oxide-semiconductor (MOS) transistor and one P-MTJ device. This circuit structure makes it possible to implement a compact nonvolatile CAM cell circuit with 1.25 m 2 of a cell size in a 0.14 m complementary MOS (CMOS)/P-MTJ process. Moreover, the equality-search operation in a bit-serial fashion is used for great reduction of the activity rate in the proposed CAM cell array, since most of the mismatched words in the CAM are detected by just several higher bits of comparison results in the word circuits. By applying a bit-level fine-grained power gating scheme, a fabricated 64-bit Â 128-word nonvolatile CAM achieves high density with maintaining low search energy under 3.1% of activity rate in the cell array. #